Abstract: A current reference circuit is disclosed. A small startup current is defined as the base current into a bipolar transistor with its collector-emitter path connected in series with a resistor between the power supply voltage and ground. This startup current is conducted via a diode-connected MOS transistor in a first leg of a current mirror. Temperature compensation is maintained by a reference leg in the current mirror that includes a bipolar transistor having an emitter area N times larger than that of a bipolar transistor in a second leg of the current mirror, to establish a temperature-compensated current in the reference leg. A compensation capacitor connected between the collector and base of a bipolar transistor in the first leg suppresses oscillation, and can be modest in size due to the Miller effect.

Abstract: A method for actuating an amplifier to generally eliminate a pop is provided. Accordingly, a plurality of current sources is actuated in an input stage, and a plurality of bias voltages are applied to the input stage. After a predetermined period after the step of applying a plurality of bias voltages to the input stage and the step of actuating a plurality of current sources in an input stage, a control circuit is actuated, and a transistor within a control amplifier stage is turned on at a predetermined rate.

Abstract: A method for actuating an amplifier to generally eliminate a pop is provided. Accordingly, a plurality of current sources is actuated in an input stage, and a plurality of bias voltages are applied to the input stage. After a predetermined period after the step of applying a plurality of bias voltages to the input stage and the step of actuating a plurality of current sources in an input stage, a control circuit is actuated, and a transistor within a control amplifier stage is turned on at a predetermined rate.

Abstract: A current reference circuit is disclosed. A small startup current is defined as the base current into a bipolar transistor with its collector-emitter path connected in series with a resistor between the power supply voltage and ground. This startup current is conducted via a diode-connected MOS transistor in a first leg of a current mirror. Temperature compensation is maintained by a reference leg in the current mirror that includes a bipolar transistor having an emitter area N times larger than that of a bipolar transistor in a second leg of the current mirror, to establish a temperature-compensated current in the reference leg. A compensation capacitor connected between the collector and base of a bipolar transistor in the first leg suppresses oscillation, and can be modest in size due to the Miller effect.

Abstract: A switching mode power supply utilizing an analog sampled data system in the feedback control loop in which the coefficients of the sampled data system are change by reprogramming a programmable nonvolatile memory when external LC values vary.

Abstract: A spare wheel assembly including a frame having opposed ends. A wheel hub is secured to one end of the frame. A pair of mounting brackets, configured for attachment to the leaf springs of a trailer, is pivotally secured to the frame. One of the mounting brackets is secured to the end of the frame not bearing the wheel hub and the other one of the mounting brackets is secured to the frame between the wheel hub and the other one of the mounting brackets. A wheel is secured to the wheel hub.

Abstract: A fully differential amplifier slew rate boosting scheme for use with an amplifier having a closed-loop gain very near unity or less has the first plates of the compensation capacitors 50 and 52 conventionally coupled to internal high impedance gain nodes 40 and 42, but has the other plates of the compensation capacitors 50 and 52 unconventionally driven with the input signal IN+ and IN−. The voltages appearing across the compensation capacitors 50 and 52 in response to changes in the input signal is significantly less than that achieved using conventional compensation architectures where the other plates of the compensation capacitors are coupled to ground. Since little current is now required to charge the compensation capacitors 50 and 52, the input stage tail current no longer limits the slew rate.

Abstract: A circuit simulator is provided for simulating the operation of a circuit in the time domain by accounting for the physical fluctuation (noise) in the time domain. Each of the components (14) in the matrix (10) has associated therewith an active current generator which can be simulated by the simulator in the time domain. In parallel with this active current generator, a stochastic (random) process current generator is provided. This stochastic current generator for each element will utilize a Gaussian random number generator (with 0 mean and a variance equal to 1) that is scaled by the standard deviation (square root of the variance) of the physical noise process that exists within the device. Additionally, this Gaussian random number generator is scaled by a factor that accounts for the time step or discrete operation of the noise simulator.

Abstract: High performance digital transistors (140) and analog transistors (144) are formed at the same time. The digital transistors (140) include pocket regions (134) for optimum performance. These pocket regions (134) are partially or completely suppressed from at least the drain side of the analog transistors (144) to provide a flat channel doping profile on the drain side. The flat channel doping profile provides high early voltage and higher gain. The suppression is accomplished by using the HVLDD implants for the analog transistors (144).

Abstract: A differential voltage sense circuit has a fuse placed in one upper leg of a resistance bridge while the remaining upper leg (sense leg) employs a resistor constructed of doped poly or poly silicide or constructed of the doped silicon that forms the N-well or P-well in CMOS process. The lower legs each have a switch selected from a pair of matched switches. A comparator, latch and combinational logic sense the state of the fuse in the resistance bridge and latch the state information before the switches can operate to stop the flow of current in the resistance bridge. The differential voltage sense circuit can operate at low voltage levels compatible with advanced CMOS processes.

Abstract: A low-pass filter circuit includes: a first compound transistor device (22) and (24) coupled between an input node (30) and an output node (32); a first transistor (20) coupled to the input node (30), a gate of the first transistor (20) is coupled to a drain of the first transistor (20); a second compound transistor device (36) and (38) coupled between a gate of the first compound transistor device (22) and (24) and the gate of the first transistor (20); a second transistor (34) coupled to the first transistor (20) and having a gate coupled to a gate of the second compound transistor device (36) and (38), the gate of the second transistor (34) is coupled to a drain of the second transistor (34); a current source (26) coupled to the drain of the second transistor (34); a first capacitor (C1) coupled to the output node (32); and a second capacitor (C2) coupled to the gate of the first compound transistor device (22) and (24).

Abstract: A circuit for reducing speaker “pops” and “clicks” during power on and power off transitions of an op amp driver. The circuit includes an op amp 14 having a first input terminal adapted to be coupled to an input signal and a second input terminal adapted to be coupled to a reference potential. A speaker 22 is capacitively coupled to the output terminal of the op amp 14. Also included are a first current source 26 for coupling a first bias current to the op amp, and a second current source 24 for coupling a second bias current to the op amp, the first bias current being much greater than said second bias current. A switch 28, coupled between the op amp 14 and the first current source 26, is responsive to a mode control signal PWDN(bar) for enabling and inhibiting flow of the first bias current to the op amp 14. In a preferred embodiment, the op amp is an integrated circuit device, and is a metal oxide semiconductor (MOS) circuit.

Abstract: Analog to digital conversion circuitry (800) is disclosed, comprising multiple quantization circuits (802), having a quantization resistor (814, 816, 818, 820) coupled between inputs of adjacent quantization circuits, wherein each quantization circuit comprises an input source follower circuit (804) having an input coupled to an analog voltage input and an output, an output source follower circuit (812) having an input and an output coupled to a digital voltage output (822, 824, 826, 828), a base transistor (836) having a first terminal coupled to the output of said input source follower circuit, a reset transistor circuit (806) coupled to said first terminal and adapted to selectively ground said first terminal responsive to an external signal, a resonant tunneling diode structure (810) coupled at a first end to a second terminal of said base transistor and at a second end to ground, and a dynamic hysteresis loading circuit (808) coupled to a third terminal of said base transistor and to the input of said ou

Abstract: A fuse trim circuit includes: a fuse 40; and a logic gate 55 having a first input coupled to the fuse 40 and a second input coupled to a logic code such that the logic code bypasses the fuse 40 to avoid prestressing the fuse 40.

Abstract: A resistive element including a P-channel MOS device (101, 401, 402, 608a-608c) having a first and second current carrying electrodes, and a gate. The first current carrying electrode forms a first impedance terminal and the second current carrying electrode forms a second impedance terminal. A bias circuit (103, 104, 105, 106) coupled to the first current carrying electrode and gate of the P-channel MOS device (101, 401, 402, 608a-608c). The bias circuit (103, 104, 105, 106) generates a voltage less than the threshold voltage of the P-channel MOS device (101, 401, 402, 608a-608c).

Abstract: An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge on either of the capacitors (14) or (16) is equal to or greater than a reference voltage input to the differential pairs (39).

Abstract: An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge on either of the capacitors (14) or (16) is equal to or greater than a reference voltage input to the differential pairs (39).

Abstract: A circuit includes a first transistor M.sub.1 ; a second transistor M.sub.2 having a gate coupled to a gate of the first transistor M.sub.1 and a source coupled to a source of the first transistor M.sub.1 ; a third transistor M.sub.3 having a source coupled to a drain of the first transistor M.sub.1 and a drain coupled to a current input I.sub.b, the drain of the third transistor M.sub.3 is coupled to the gate of the first transistor M.sub.1 ; a fourth transistor M.sub.4 having a source coupled to a drain of the second transistor M.sub.2, a gate coupled to a gate of the third transistor M.sub.3, and a drain coupled to a supply node V.sub.DD ; and a variable voltage input V.sub.x coupled to the gate of the third transistor M.sub.3.

Abstract: A voltage generation circuit (10) is provided including a first plurality of transistors (12, 14, 16, 18) having source/drain paths coupled in series to establish a first current path between a first voltage rail and a second voltage rail, the first transistors (12, 14, 16, 18) matched to provide a preselected intermediate voltage at a node (A) along the first current path. A second plurality of transistors (20, 22, 24, 26) are provided having source/drain paths coupled in series to establish a second current path between the voltage rails, and coupled to the first transistors (12, 14, 16, 18) such that current flow in the second current path selected ones of mirrors current flow in the first current path, the second plurality of transistors (20, 22, 24, 26) matched to provide a voltage substantially equal to the intermediate voltage at a node (B) along the second current path.

Abstract: A CMOS on chip mid-rail voltage generation circuit is provided for an analog ground reference. A voltage divider establishes a current path between the high and low rail, and supplies a mid-level voltage to one input of a differential amplifier. A pair of series connected field effect transistors are also connected between the high and low voltage rails, with their common connection providing the input to the other input of the differential amplifier. A pair of open loop output transistors are also coupled in series between the high and low voltage rails, and each has their gate coupled to one of the series connected pair, and is also matched to that pair.