Patents by Inventor James R. Hightower

James R. Hightower has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6927494
    Abstract: A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: August 9, 2005
    Assignee: LSI Logic Corporation
    Inventors: Derryl D. J. Allman, James R. Hightower, Phonesavanh Saopraseuth
  • Publication number: 20030186531
    Abstract: A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels.
    Type: Application
    Filed: March 27, 2003
    Publication date: October 2, 2003
    Applicant: LSI Logic Corporation
    Inventors: Derryl D.J. Allman, James R. Hightower, Phonesavanh Saopraseuth
  • Patent number: 6576544
    Abstract: A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: June 10, 2003
    Assignee: LSI Logic Corporation
    Inventors: Derryl D. J. Allman, James R. Hightower, Phonesavanh Saopraseuth
  • Patent number: 4170095
    Abstract: An apparatus having a plurality of supports adapted to receive containers with portions of the containers spaced from their respective supports, an assembly mounting the supports in spaced relation to a first path of travel for movement along a second path of travel approaching the first path of travel, and a control system for individually detecting when the portions of the containers reach the first path of travel and thereupon terminating movement of their respective supports along the second path of travel.
    Type: Grant
    Filed: March 27, 1978
    Date of Patent: October 9, 1979
    Assignee: S.W.F. Machinery, Inc.
    Inventor: James R. Hightower