Abstract: Apparatus and methods disclosed herein operate to reducing switching artifacts associated with dynamic element matching by sorting a set of unit elements to establish a priority order of selection of a subset of the set of unit elements to use in a next single-sample integration operation. Sorting is achieved by demoting unit elements during the sorting if a usage value associated with the unit element is greater than or equal to a maximum allowable usage spread parameter value. A unit element is promoted during the sorting if a usage value associated with the unit element is less than the maximum allowable usage spread parameter value and the unit element was used in an immediately previous single-sample integration operation.

Abstract: Apparatus and methods disclosed herein operate to reducing switching artifacts associated with dynamic element matching by sorting a set of unit elements to establish a priority order of selection of a subset of the set of unit elements to use in a next single-sample integration operation. Sorting is achieved by demoting unit elements during the sorting if a usage value associated with the unit element is greater than or equal to a maximum allowable usage spread parameter value. A unit element is promoted during the sorting if a usage value associated with the unit element is less than the maximum allowable usage spread parameter value and the unit element was used in an immediately previous single-sample integration operation.

Abstract: Devices, systems, and methods for providing delta-sigma modulation in conjunction with analog-to-digital or digital-to-analog signal conversion are disclosed. The delta-sigma modulator and delta-sigma converter include dynamically-scalable coefficients, which, at relatively low signal amplitudes, allow the delta-sigma modulator and delta-sigma converter to modulate the signals using a first noise transfer function and, at relatively greater signal amplitudes, allow the delta-sigma modulator and delta-sigma converter to modulate the signals using a second noise transfer function.

Abstract: The present invention is a digital dynamic compression or automatic gain control (AGC) (10) adapted for use in high quality audio and hearing aids applications. An efficient digital AGC design employs two compact ROM-based tables (ROM_CSD, ROM_SPL) in addition to two comparators (COMP_A, COMP_B) and several registers (REG_A, REG_B, ADDR_A, ADDR_B). While one ROM stores the values of discrete input signal levels, the other contains gain codes based on a canonical signed digit (CSD) coding approach that leads to a very simple gain multiplier (20). In many cases an extremely compact table for gain values can be achieved by reusing a single small-size ROM that behaves like one that is several time larger. Two design examples are shown to expound the insights of the new digital AGC design. For the less-than-half-dB-gain-step cases only two adders are required for the multiplier whereas just three adders are needed in the situations with less than quarter-dB gain steps.

Abstract: Devices, systems, and methods for providing delta-sigma modulation in conjunction with analog-to-digital or digital-to-analog signal conversion are disclosed. The delta-sigma modulator and delta-sigma converter include dynamically-scalable coefficients, which, at relatively low signal amplitudes, allow the delta-sigma modulator and delta-sigma converter to modulate the signals using a first noise transfer function and, at relatively greater signal amplitudes, allow the delta-sigma modulator and delta-sigma converter to modulate the signals using a second noise transfer function.

Abstract: A sigma-delta converter having dynamic dithering that reduces or removes idle-channel tones and increase linearity of the converter. The dither is differentiated in multiple orders before being applied to the converter quantizer. The differentiation order and the amplitude of the dither are determined dynamically based on the input signal amplitude in order to obtain the most effectiveness of dithering. The dynamic dither can be used in both analog-to-digital and digital-to-analog converters.

Abstract: A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The master and slave transparent latches have opposite transparent polarities when in a functional mode and have the same polarities (e.g., positive level sense) when in a scan mode. The transparent polarity of a transparent latch defines the state of a clock to that latch for which the transparent latch is transparent.

Abstract: An improved digital interface circuit that allows a plurality of data streams and other digital information to be output over a single channel. The digital interface circuit includes a plurality of data inputs, at least one control input, at least one clock input, and a single serial bit output. The digital interface circuit receives respective input data streams at the data inputs, receives digital control information at the control input, and receives a clock signal at the clock input. The control information is an N-bit data stream having a data rate of 1/N times the rate of the input data streams (N?1). The digital interface circuit generates a frame synchronization signal for providing framing for the N-bit data stream, and time-multiplexes the data and control information over the single serial bit output.

Abstract: The present invention discloses a level shifter circuit (20) comprising a serially coupled first device (M3) and second device (M5), a serially coupled third device (M4) and fourth device (M6), a parallel coupled first pull-up device (M9) and second pull-up device (M10), a plurality of nodes (N1–N4), and a set-reset latch (22) comprising a first gate (I1) and a second gate (I2), wherein the first device (M3) is coupled to the first pull-up device (M9) via a first one (N1) of the plurality of nodes, wherein the second device (M5) is coupled to the first gate (I1) via a third one (N3) of the plurality of nodes, wherein the third device (M4) is coupled to the second pull-up device (M10) via a second one (N2) of the plurality of nodes, and wherein the fourth device (M6) is coupled to the second gate (I2) via a fourth one (N4) of the plurality of nodes.

Abstract: The present invention accepts timing and clock signals with a desired frequency and undesired duty cycle CLKIN, and outputs a clock signal CLKOUT with the desired frequency and desired duty cycle. If the clock signal is known to have a duty cycle of greater than 50%, one exemplary embodiment of the present invention delays the rising edge of the clock signal so as to produce a clock signal with a 50% duty cycle. One exemplary embodiment of the present invention comprises a charge pump integrator (102) configured in a feedback loop, the output of the charge pump integrator (102) operable as a controlling node to delay inverter (115). If the clock signal CLKIN at the input of the circuit has a duty cycle of greater than 50%, then the charge pump integrator (102) will, through PBIAS, cause delay inverter 115 to delay of the rising edge of CLKIN through delay inverter (115). The charge pump integrator, through PBIAS, drives the duty cycle of the clock signal towards 50%.

Abstract: A common-mode noise reduction circuit (20) adapted to receive a DIN input (?1, 0, +1), such as from a sigma-delta modulator (12), and provide alternating outputs (DoutP, DoutM) such as to reduce the common-mode noise of an H-bridge (14). A zero detect circuit (26), a pattern generator (28) and a level generator circuit (24) provide that the outputs DoutP and DoutM are either both logic 1 or both logic 0, such as to lower the common-mode noise level by a device, such as a H-bridge (14). This circuitry (20) places a zero in the transfer function of the H-bridge (14) to reduce the common-mode noise, whereby high pass filters shape the noise out-of-band in an over sampled system.

Abstract: An improved digital interface circuit that allows a plurality of data streams and other digital information to be output over a single channel. The digital interface circuit includes a plurality of data inputs, at least one control input, at least one clock input, and a single serial bit output. The digital interface circuit receives respective input data streams at the data inputs, receives digital control information at the control input, and receives a clock signal at the clock input. The control information is an N-bit data stream having a data rate of 1/N times the rate of the input data streams (N≧1). The digital interface circuit generates a frame synchronization signal for providing framing for the N-bit data stream, and time-multiplexes the data and control information over the single serial bit output.

Abstract: In a microprocessor, a method for providing a sample-rate conversion (“SRC”) filter on an input stream of sampled data provided at a first rate, to produce an output stream of data at a second rate different from the first rate. The input stream of sampled data is operated on with a first low-order interpolation filter routine to produce a first stream of intermediate data. The first stream of intermediate data is operated on with a first simplified interpolation filter routine, having a substantially small number of operations to calculate the coefficients thereof, to produce a second stream of intermediate data. The second stream of intermediate data is operated on with a first decimating filter routine to produce the output stream of data.

Abstract: An improved sigma-delta modulation technique that may be employed in a sigma-delta Digital-to-Analog Converter (DAC) to convert digital signals into corresponding analog signals over a wide signal range and with high linearity. The sigma-delta DAC comprises a sigma-delta modulator including a variable quantizer and a quantizer controller, and an internal DAC. The sigma-delta modulator adaptively quantizes the digital input signal to a first number p of quantization levels. Next, the quantizer controller controls the variable quantizer to correlate the p quantization levels to the amplitude of the digital input signal, thereby generating a second number q of quantization levels. The internal DAC then receives the q quantization levels from the variable quantizer one group of p levels at a time, and produces an analog output signal therefrom that corresponds to the digital input signal.

Abstract: The present invention accepts timing and clock signals with a desired frequency and undesired duty cycle CLKIN, and outputs a clock signal CLKOUT with the desired frequency and desired duty cycle. If the clock signal is known to have a duty cycle of greater than 50%, one exemplary embodiment of the present invention delays the rising edge of the clock signal so as to produce a clock signal with a 50% duty cycle. One exemplary embodiment of the present invention comprises a charge pump integrator (102) configured in a feedback loop, the output of the charge pump integrator (102) operable as a controlling node to delay inverter (115). If the clock signal CLKIN at the input of the circuit has a duty cycle of greater than 50%, then the charge pump integrator (102) will, through PBIAS, cause delay inverter 115 to delay of the rising edge of CLKIN through delay inverter (115). The charge pump integrator, through PBIAS, drives the duty cycle of the clock signal towards 50%.

Abstract: An improved sigma-delta modulation technique that may be employed in a sigma-delta Digital-to-Analog Converter (DAC) to convert digital signals into corresponding analog signals over a wide signal range and with high linearity. The sigma-delta DAC comprises a sigma-delta modulator including a variable quantizer and a quantizer controller, and an internal DAC. The sigma-delta modulator adaptively quantizes the digital input signal to a first number p of quantization levels. Next, the quantizer controller controls the variable quantizer to correlate the p quantization levels to the amplitude of the digital input signal, thereby generating a second number q of quantization levels. The internal DAC then receives the q quantization levels from the variable quantizer one group of p levels at a time, and produces an analog output signal therefrom that corresponds to the digital input signal.

Abstract: The present invention discloses a level shifter circuit (20) comprising a serially coupled first device (M3) and second device (M5), a serially coupled third device (M4) and fourth device (M6), a parallel coupled first pull-up device (M9) and second pull-up device (M10), a plurality of nodes (N1-N4), and a set-reset latch (22) comprising a first gate (I1) and a second gate (I2), wherein the first device (M3) is coupled to the first pull-up device (M9) via a first one (N1) of the plurality of nodes, wherein the second device (M5) is coupled to the first gate (I1) via a third one (N3) of the plurality of nodes, wherein the third device (M4) is coupled to the second pull-up device (M10) via a second one (N2) of the plurality of nodes, and wherein the fourth device (M6) is coupled to the second gate (I2) via a fourth one (N4) of the plurality of nodes.

Abstract: A common-mode noise reduction circuit (20) adapted to receive a DIN input (−1, 0, +1), such as from a sigma-delta modulator (12), and provide alternating outputs (DoutP, DoutM) such as to reduce the common-mode noise of an H-bridge (14). A zero detect circuit (26), a pattern generator (28) and a level generator circuit (24) provide that the outputs DoutP and DoutM are either both logic 1 or both logic 0, such as to lower the common-mode noise level by a device, such as a H-bridge (14). This circuitry (20) places a zero in the transfer function of the H-bridge (14) to reduce the common-mode noise, whereby high pass filters shape the noise out-of-band in an over sampled system.

Abstract: An infinite impulse response (IIR) digital filter and method of performing the same is disclosed. The digital filter may be realized by way of a programmable logic device, such as a digital signal processor (75), or alternatively by way of dedicated logic including adders (44, 48, 50, 54, 58, 62, 66, 70, 72) and shifters (46, 52, 56, 60, 64). In either case, addition operations (34) are interleaved among first and second output sample values (yn−1, yn−2), so that the resulting addition (30; 72; 215; 320) may be carried out with adder circuitry of the same precision as the signal input (xn) and signal output (yn). Carry control circuitry (76, 78, 80, 82, 84, 88; 217; 317) is provided to efficiently incorporate magnitude truncation quantization.

Abstract: A circuit simulator is provided for simulating the operation of a circuit in the time domain by accounting for the physical fluctuation (noise) in the time domain. Each of the components (14) in the matrix (10) has associated therewith an active current generator which can be simulated by the simulator in the time domain. In parallel with this active current generator, a stochastic (random) process current generator is provided. This stochastic current generator for each element will utilize a Gaussian random number generator (with 0 mean and a variance equal to 1) that is scaled by the standard deviation (square root of the variance) of the physical noise process that exists within the device. Additionally, this Gaussian random number generator is scaled by a factor that accounts for the time step or discrete operation of the noise simulator.