Abstract: Systems and methods supporting high performance real time pattern recognition by including time and regional multiplexing using high bandwidth, board-to-board communications channels, and 3D vertical integration. An array of processing boards can each be coupled a rear transition board, the array achieving time and regional multiplexing using high bandwidth board-to-board communications channels and 3D vertical integration.

Abstract: Systems and methods supporting high performance real time pattern recognition by including time and regional multiplexing using high bandwidth, board-to-board communications channels, and 3D vertical integration. An array of processing boards can each be coupled a rear transition board, the array achieving time and regional multiplexing using high bandwidth board-to-board communications channels and 3D vertical integration.

Abstract: A two-to-one multiplexor comprises a first data input configured to hold data provided from a first preceding asynchronous pipeline stage and a second data input configured to hold data provided from a second preceding asynchronous pipeline stage, a 4-phase bundled data protocol facilitating communication between the first and the second data inputs and the first and second preceding asynchronous pipeline stage, an arbitration unit connected to the first data input and the second data input, and configured to select which of the data from the first and the second data inputs is released, a request release unit, and a reset unit wherein the arbitration unit, the request release unit, and the reset unit implement and complete a second 4-phase bundled data protocol facilitating communication with a succeeding asynchronous pipeline stage for transmission of the data chosen by the arbitration unit thereby providing asynchronous multiplexing of the data.

Abstract: A two-to-one multiplexor comprises a first data input configured to hold data provided from a first preceding asynchronous pipeline stage and a second data input configured to hold data provided from a second preceding asynchronous pipeline stage, a 4-phase bundled data protocol facilitating communication between the first and the second data inputs and the first and second preceding asynchronous pipeline stage, an arbitration unit connected to the first data input and the second data input, and configured to select which of the data from the first and the second data inputs is released, a request release unit, and a reset unit wherein the arbitration unit, the request release unit, and the reset unit implement and complete a second 4-phase bundled data protocol facilitating communication with a succeeding asynchronous pipeline stage for transmission of the data chosen by the arbitration unit thereby providing asynchronous multiplexing of the data.

Abstract: CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.