Abstract: A level shift circuit with high switching speed and low power dissipation is described. The circuit includes two short channel transistors, two long channel transistors, and two switching transistors. Short channel transistors are arranged to receive a high input voltage presenting relatively low impedance and low capacitance. Long channel transistors are arranged to receive a first voltage from the short channel transistors and provide an output voltage and an inverted output voltage, which are also employed to control the short channel transistors. A first switching transistor of the switching circuit enables the short channel and the long channel circuits to provide the output voltage based on a low input voltage and a logic input voltage. A second switching transistor enables the same circuits to provide the inverted output voltage based on the logic input voltage.

Abstract: A method and circuit to adjust timing between received differential data and clock signals to compensate for differences between transmission paths of data and clock signals. According to one embodiment, a timing adjustment circuit includes a decoder, a differential delay stage and a converter stage. The decoder is arranged to select one of the differential tri-state buffers, which provides the signal with a selected delay to a differential-to-single-ended converter. The converter provides properly a timing-adjusted signal to other circuits for further processing. Two current sources may be employed instead of resistive loads for the converter stage resulting in increased operating frequency and decreased power dissipation.

Abstract: A differential amplifier circuit achieves offset cancellation by supplying an offset correction current from a current copier circuit to the output of the differential amplifier. The current copier is programmed by closing a first switch to short the differential input terminals of the amplifier, by opening a second switch to break the feedback loop of the amplifier, and by closing a third switch to allow the current copier to sense the offset output voltage at the output of the amplifier. The current copier generates an equal and opposite offset cancellation current which is summed with the offset current from the amplifier. The current copier circuit includes a storage capacitor for storing a voltage required to produce such offset cancellation current. After programming the storage capacitor, the third switch is opened, the first switch is opened, and the second switch is closed for normal operation.