Abstract: A data transceiver includes a transmitter connected at one end of a data transmission line and a receiver connected at the other end of the data transmission line. At least some portions of the transceiver are formed in CMOS. A temperature compensation circuit is connected to selected components of the transceiver to correct for temperature-induced variations in currents through those components. The temperature compensation circuit includes a pair of transistors connected, respectively, in parallel conduction paths. The respective width-to-length ratios of the channels of the transistors are unequal, and their gates are tied together. The current through the larger transistor varies directly with temperature, and this current is reflected in a current mirror transistor that is connected to the shorted gates of the transistor pair.

Abstract: A driver for providing binary signals from a data system to a transmission line is disclosed. The driver includes a first field-effect transistor (FET) coupled between an output node and ground for conducting current from the output node to ground. The output node is connectable to the transmission line. An initial charging stage provides an initial charging current to the gate of the first FET for a period of time not to exceed an initial charging time period. The initial charging time period has a length approximately equal to a period of time necessary to increase the gate voltage of the first FET from ground to the threshold voltage of the first FET. A main charging stage provides a main charging current to the gate of the first FET for a period of time not to exceed a main charging time period. A discharging stage provides a discharging current from the gate of the first FET to ground.

Abstract: A driver for providing binary signals from a data system to a transmission line is disclosed. The driver includes a first field-effect transistor (FET) coupled between an output node and ground for conducting current from the output node to ground. The output node is connectable to the transmission line. A first input stage conducts current from a first voltage supply to the gate of the first FET. The first input stage includes a voltage sensing amplifier for comparing a reference voltage to the voltage potential of the output node and for controlling the amount of current conducted to the gate of the first FET in response to the comparison. A second input stage conducts current from the gate of the first FET to ground.

Abstract: A differential mode voltage controlled oscillator (VCO) includes an odd number of delay cells. Each delay cell has a pair of input terminals and a pair of output terminals with the input terminals of each delay cell being connected to the output terminals of a preceding delay cell in a ring. Each delay cell has a delay time for inverting a complementary pair of signals from which a clock signal is derived. A positive temperature coefficient voltage-to-current converter receives the control voltage of the VCO and controls the maximum currents (and therefore the delays) of the delay cells. A pair of cross-coupling transistors in each delay cell keeps the signals on the output terminals out of phase (complementary). The cross-coupling transistors have sizes which maximize gain of the delay cells at the threshold voltages of the cross-couple transistor and thereby increase output voltage swing at high frequencies.

Abstract: The driver stage of a high speed multi-channel data transceiver in accordance with the present invention includes a bias voltage regulator that regulates base drive for each transceiver driver stage to achieve fast and stable propagation delay over varying supply and temperature conditions. An input capacitor connected to the voltage bias input line provides instant base drive to the output driver for fast turn-on without adding DC current. Two pairs of Miller capacitor transistors connected between the transceiver's driver stage data input and the collector of the output driver control driver output slew rate. A discharge capacitive network connected to the base of the output driver provides an instant discharge path when the driver is disabled.On the receiver side, an ECC-to-TTL converter stage reduces node capacitance and provides fast turn-off. A TTL output buffer that uses the backplane transceiver logic ground as ground consumes zero power when the receiver is in the high impedance state.

Abstract: A multi-bit latch transceiver is designed to meet the IEEE 1194.1 standard for backplane transceiver logic as specified in the IEEE 896.2 Futurebus+ specification. The latch transceiver features support for live insertion, low skew, controlled rise/fall time (2ns-5ns) and glitch free power-up/down protection. The transceiver utilizes on-chip latches and a built-in bandgap reference that provides very accurate thresholds. Unique slave stage logic in the transceiver's driver stage provides preset input conditions to the slave latch such that data is instantly clocked to the driver output when the driver is enabled, thus reducing propagation delay.

Abstract: An energy dissipation circuit for protecting a semiconductor integrated circuit from electrostatic discharge (ESD). The dissipation circuit provides an energy dissipation path between any combination of two pins of the semiconductor integrated circuit to be protected.

Abstract: A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.

Abstract: A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.

Abstract: A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.

Abstract: The present invention is an improved subscriber line interface circuit which allows fast detection of an off-hook signal in the presence of a ringing signal during an answer mode while also permitting fast detection of dialing pulses during a calling mode. A programmable filter is used in the supervision circuit of the SLIC to allow the cutoff frequency of the filter to be varied so that the 20 Hz ringing signal will be attenuated during a ringing sequence and dialing pulse rates up to 20 Hz will be passed by the filter during the calling mode. A clamping amplifier is used to clamp the received signal to a maximum of 1.5 times the loop threshold current. This eliminates the large variations in the rise and fall times of the pulse dialing signal due to variations in the loop current caused by varying impedances of the telephone line. The filter is programmed by using an analog switch to bypass certain filter elements.

Abstract: The present invention is an improved active load which eliminates the current imbalance between the collectors of the emitter-coupled input transistors. The circuit includes a pair of first and second emitter-coupled transistors with their collectors coupled to a current source which supplies substantially equal currents to the collectors of the two transistors. The collector of one of the emitter-coupled transistors is coupled to the base of a third output transistor. A fourth transistor is coupled between the collector of the output transistor and the supply voltage. Finally, the circuit includes means for supplying the base current to the fourth transistor such that the base current of the fourth transistor and the third output transistor are substantially equal and the collector currents of the first and second emitter-coupled transistors remain substantially equal, resulting in negligible offset current and high open loop gain.

Abstract: A power transistor array integrated circuit includes an array of transistors, each having an electrode connected in common to a conductive line forming a part of the integrated circuit. The electrodes of the transistors are spaced along the conductive line and have a decreasing length in a given direction along the conductive line and have a decreasing length in a given direction along the conductive line. The conductive line has a corresponding increasing width in the given direction. The decrease in length of the electrode and the increase in width of the conductive line are such that the electrodes and the conductive line form a generally rectangular shape. Differences in turn-on voltage for the transistors resulting from the differences in their electrode length tend to compensate for voltage drop in the conductive line, thus giving uniform outputs from the transistors in the array.

Abstract: A temperature-compensated reference voltage circuit includes a transistor having a positive temperature coefficient of current. A circuit for establishing a predetermined current in the positive-temperature-coefficient-of-current transistor is connected to that transistor. A predetermined resistance serially connects the positive-temperature-coefficient-of-current transistor with a transistor having negative temperature coefficient of base-to-emitter voltage. The temperature-compensated reference voltage is established between the transistors. The temperature-compensated reference voltage circuit is particularly useful in a supply voltage sense amplifier circuit for thermal printhead drive transistors or other load elements. The sense amplifier circuit includes a circuit for comparing the reference voltage and a supply voltage. An output is adapted to be connected to a load for receiving the supply voltage.

Abstract: A high speed driver for providing high-current and high-voltage output levels suitable for driving MOS circuits, such as MOS RAMs from standard TTL input signals. Novel circuitry in the driver provides very high speed signal switching and a power-saving feature prevents MOS supply current drain by the circuit when TTL power has been turned off.