Patents by Inventor James R. Loomis

James R. Loomis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5421507
    Abstract: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au--Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, mulilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: June 6, 1995
    Assignee: International Business Machines Corporation
    Inventors: Charles R. Davis, Richard Hsiao, James R. Loomis, Jae M. Park, Jonathan D. Reid
  • Patent number: 5403420
    Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: April 4, 1995
    Assignee: International Business Machines Corporation
    Inventors: Thomas P. Gall, James R. Loomis, David B. Stone, Cheryl L. Tytran, James Wilcox
  • Patent number: 5379193
    Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: January 3, 1995
    Assignee: International Business Machines Corporation
    Inventors: Thomas P. Gall, James R. Loomis
  • Patent number: 5280414
    Abstract: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, multilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.
    Type: Grant
    Filed: June 11, 1990
    Date of Patent: January 18, 1994
    Assignee: International Business Machines Corp.
    Inventors: Charles R. Davis, Richard Hsiao, James R. Loomis, Jae M. Park, Jonathan D. Reid
  • Patent number: 4969979
    Abstract: Substantially nonconductive or semiconductive surfaces of through holes can be electroplated directly, without an intervening non-electrolytic metallization, by a stepwise process which includes the application to the through holes of a polyelectrolyte surfactant in solution in combination with the application of a conductive metal containing material.
    Type: Grant
    Filed: May 8, 1989
    Date of Patent: November 13, 1990
    Assignee: International Business Machines Corporation
    Inventors: Bernd K. Appelt, Perminder Bindra, Robert D. Edwards, James R. Loomis, Jae M. Park, Jonathan D. Reid, Lisa J. Smith, James R. White
  • Patent number: 4960634
    Abstract: A composition of enhanced thermal conductivity which comprises a tetrabrominated diglycidyl ether polyepoxide; and epoxy polymer having an epoxy functionality of 3.5 to 6; zinc oxide and curing agents; and use thereof.
    Type: Grant
    Filed: March 14, 1990
    Date of Patent: October 2, 1990
    Assignee: International Business Machines Corporation
    Inventors: Christina M. Boyko, Craig N. Johnston, James R. Loomis, Carl E. Samuelson, Ricahrd A. Schumacher