Abstract: Edge-emitting laser chip wafer layouts are provided that enable a variety of tests to be performed while the chips are on the wafer, including side-mode suppression ratio (SMSR) tests. The laser chip wafer layouts include turning mirrors that direct light passing out of at least one of the facets of the chips away from the wafer. Directing the light out of the wafer in this manner allows external test and measurement equipment to perform SMSR testing on the chips prior to singulation.

Abstract: A thin conformal passivating dielectric film is deposited by ECR-CVD on an IC chip comprising semiconductor devices each of which includes a sub-micron-width irregularly shaped gate electrode. A protective layer of patterned resist is formed overlying each passivated device. Additional dielectric material is then deposited by ECP-CVD, at a temperature below the glass transition temperature of the resist, on the surface of the chip. Subsequently, in a lift-off step, the patterned resist together with the additional dielectric material overlying the resist is removed from the chip.