Patents by Inventor James R. Lundberg

James R. Lundberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10401427
    Abstract: A scannable data synchronizer including an input circuit, first and second pass gates, first and second inverters, and a gate controller. The input circuit drives the data nodes to opposite logic states in response to an asynchronous input data signal in a normal mode and in response to scan data in a scan test mode. Each pass gate is coupled between one of the data nodes and a corresponding one of the capture nodes, and each has at least one control terminal. The inverters are cross-coupled between the second capture nodes. The gate controller can keep the pass gates at least partially open during a metastable condition of the capture nodes, and can close the pass gates when both capture nodes stabilize to opposite logic states. In the scan test mode, the scan data is used to test the latch or register functions of the scannable data synchronizer.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: September 3, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: James R. Lundberg
  • Patent number: 10133701
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure, when an update signal is asserted, the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: November 20, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Vanessa Canac, James R. Lundberg
  • Patent number: 10133700
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus, the apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal, and is configured to generate a first value on a lag bus that indicates the time.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: November 20, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Vanessa Canac, James R. Lundberg
  • Patent number: 10079047
    Abstract: A method is provided that compensates for misalignment on a synchronous data bus.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: September 18, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Vanessa Canac, James R. Lundberg
  • Patent number: 10079046
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second signal, where the replica radial distribution element comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The bit lag control element has delay lock control and a gray encoder.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: September 18, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Vanessa Canac, James R. Lundberg
  • Publication number: 20180143247
    Abstract: A scannable data synchronizer including an input circuit, first and second pass gates, first and second inverters, and a gate controller. The input circuit drives the data nodes to opposite logic states in response to an asynchronous input data signal in a normal mode and in response to scan data in a scan test mode. Each pass gate is coupled between one of the data nodes and a corresponding one of the capture nodes, and each has at least one control terminal. The inverters are cross-coupled between the second capture nodes. The gate controller can keep the pass gates at least partially open during a metastable condition of the capture nodes, and can close the pass gates when both capture nodes stabilize to opposite logic states. In the scan test mode, the scan data is used to test the latch or register functions of the scannable data synchronizer.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Inventor: JAMES R. LUNDBERG
  • Patent number: 9953002
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal when an update signal is asserted, and is configured to generate a first value on a lag bus that indicates the time.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 24, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Vanessa Canac, James R. Lundberg
  • Patent number: 9898036
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: February 20, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Vanessa Canac, James R. Lundberg
  • Patent number: 9793894
    Abstract: A data synchronizer that registers an input data signal into a clock domain of a clock signal. The data synchronizer includes in input circuit, first and second pass gates, first and second inverters, gate controller, and a register. The input circuit drives first and second data nodes to opposite logic states based on the input data signal. Each pass gate is coupled between a data node and a capture node. The inverters are cross-coupled between the capture nodes. The gate controller is capable of keeping the pass gates at least partially open during a metastable condition of the capture nodes, and closes the pass gates when the capture nodes resolve to opposite logic states. The register registers a capture node to provide a registered data output in response to the clock signal. The data synchronizer may be implemented using FinFET devices.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 17, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: James R. Lundberg
  • Patent number: 9768776
    Abstract: A data synchronizer that latches an asynchronous input data signal relative to a clock signal. The data synchronizer includes in input circuit, first and second pass gates, first and second inverters, and a gate controller. The input circuit drives first and second data nodes to opposite logic states based on the asynchronous input data signal. Each pass gate is coupled between an input data node and a capture node. The inverters are cross-coupled between the capture nodes. The gate controller is capable of keeping the pass gates at least partially open during a metastable condition of the capture nodes, and closes the pass gates when the capture nodes resolve to opposite logic states. The capture nodes may be buffered in a substantially balanced manner to provide a buffered output, and the buffered output may be registered into the clock domain. The data synchronizer may be implemented using FinFET devices.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: September 19, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: James R. Lundberg
  • Publication number: 20170110163
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second signal, where the replica radial distribution element comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The bit lag control element has delay lock control and a gray encoder.
    Type: Application
    Filed: December 23, 2016
    Publication date: April 20, 2017
    Inventors: VANESSA CANAC, JAMES R. LUNDBERG
  • Publication number: 20170109306
    Abstract: A method is provided that compensates for misalignment on a synchronous data bus.
    Type: Application
    Filed: December 23, 2016
    Publication date: April 20, 2017
    Inventors: VANESSA CANAC, JAMES R. LUNDBERG
  • Publication number: 20170103790
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus, the apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal, and is configured to generate a first value on a lag bus that indicates the time.
    Type: Application
    Filed: December 23, 2016
    Publication date: April 13, 2017
    Inventors: VANESSA CANAC, JAMES R. LUNDBERG
  • Publication number: 20170102733
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time.
    Type: Application
    Filed: December 23, 2016
    Publication date: April 13, 2017
    Inventors: VANESSA CANAC, JAMES R. LUNDBERG
  • Publication number: 20170102734
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure, when an update signal is asserted, the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time.
    Type: Application
    Filed: December 23, 2016
    Publication date: April 13, 2017
    Inventors: VANESSA CANAC, JAMES R. LUNDBERG
  • Publication number: 20170103035
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal when an update signal is asserted, and is configured to generate a first value on a lag bus that indicates the time.
    Type: Application
    Filed: December 23, 2016
    Publication date: April 13, 2017
    Inventors: VANESSA CANAC, JAMES R. LUNDBERG
  • Patent number: 9557765
    Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver that is configured to receive one of a plurality of radially distributed strobes and a data bit, and that is configured to delay registering of the data bit by a propagation time. The replica radial distribution element is configured to receive a first signal, and is configured to generate a second signal, where the replica radial distribution element comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: January 31, 2017
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Vanessa S. Canac, James R. Lundberg
  • Patent number: 9552321
    Abstract: A method for aligning signals on a bus, including: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe; receiving a first signal, and generating a second signal by employing the replicated propagation path lengths, loads, and buffering; receiving control information over a standard JTAG bus, wherein the control information indicates an amount to adjust a propagation time; and measuring the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, said measuring comprising: selecting one of a plurality of successively delayed versions of the first signal that coincides with assertion of the second signal; adjusting the propagation time by the amount prescribed by the control information to yield an adjusted propagation time; and gray encoding the adjusted propagation time to generate a value on a lag bus.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: January 24, 2017
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Vanessa S. Canac, James R. Lundberg
  • Patent number: 9552320
    Abstract: A method that compensates for misalignment on a synchronous data bus. The method includes: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe, receiving a lag pulse signal, and generating a replicated strobe signal by employing the replicated propagation path loads lengths, and buffering; measuring the time between assertion of the lag pulse signal and assertion of the replicated strobe signal; on a lag bus, generating a value that indicates the time; within a synchronous lag receiver, receiving a first one of a plurality of radially distributed strobes and a data bit, and delaying registering of the data bit by the time.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: January 24, 2017
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Vanessa S. Canac, James R. Lundberg
  • Patent number: 9450580
    Abstract: An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: September 20, 2016
    Assignee: VIA TECHNOLOGIES, INC.
    Inventor: James R. Lundberg