Abstract: A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises detecting memory address information corresponding to accessed data in a first instruction, and detecting memory address information corresponding to accessed data in a second instruction. The method further comprises comparing the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detecting, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. In addition the method comprise executing the second instruction using the accessed data from the first instruction and detecting an error from the execution of the second instruction.

Abstract: Techniques for generating a design structure for cache power reduction are described herein. In one example, a system includes logic to detect memory address information corresponding to accessed data in a first instruction, and detect memory address information corresponding to accessed data in a second instruction. The logic can also compare the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detect, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. The logic can also execute the second instruction using the accessed data from the first instruction.

Abstract: Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.

Abstract: Embodiments relate to loading data in a pipelined microprocessor. An aspect includes issuing a load request that comprises a load address requiring at least one block of data the same size as a largest contiguous granularity of data returned from a cache. Another aspect includes determining that the load address matches at least one block address. Another aspect includes, based on determining that there is an address match, reading a data block from a buffer register and sending the data to satisfy the load request; comparing a unique set id of the data block to the set id of the matching address after sending the data block; based on determining that there is a set id match, continuing the load request, or, based on determining that there is not a set id match, setting a store-forwarding state of the matching address to no store-forwarding and rejecting the load request.

Abstract: A method and system is provided that includes a setpoint monitor in communication with a controller that operates equipment according to setpoint values, each setpoint value having an associated benchmark value. The setpoint monitor receives setpoint modifications based on communication with the controller, each setpoint modification corresponding to a modification of a setpoint value to a modified value different from the associated benchmark value. A terminal in communication with the setpoint monitor displays the setpoint modifications and receives input to revert a setpoint modification from the modified value back to the associated benchmark value. The setpoint monitor communicates with the controller to revert the setpoint value associated with the setpoint modification from the modified value back to the associated benchmark value.

Abstract: A method and system is provided that includes a controller that operates at least one piece of equipment according to setpoint values and a setpoint monitor in communication with the controller. The setpoint monitor receives setpoint modifications, each setpoint modification corresponding to a modification of one of the setpoint values. The setpoint monitor calculates an expected change in energy consumption of the at least one piece of equipment for each of the setpoint modifications and ranks the setpoint modifications based on the expected change in energy consumption. A first terminal is in communication with the setpoint monitor and displays the setpoint modifications in an order based on the ranking of the setpoint modifications. The first terminal receives input for each setpoint modification of the plurality of setpoint modifications indicating approval or rejection of the setpoint modification.

Abstract: According to some embodiments, loss data may be received. The received loss data may be used to populate cells in a pivot data worksheet in a spreadsheet application workbook. At least one pivot table in at least one pivot table worksheet of the spreadsheet application workbook may be automatically created based on the pivot data worksheet. According to some embodiments, the pivot table includes cells that summarize the loss data associated with the insurance claims submitted under an insurance policy.

Abstract: Embodiments relate to loading data in a pipelined microprocessor. An aspect includes issuing a load request that comprises a load address requiring at least one block of data the same size as a largest contiguous granularity of data returned from a cache. Another aspect includes determining that the load address matches at least one block address. Another aspect includes, based on determining that there is an address match, reading a data block from a buffer register and sending the data to satisfy the load request; comparing a unique set id of the data block to the set id of the matching address after sending the data block; based on determining that there is a set id match, continuing the load request, or, based on determining that there is not a set id match, setting a store-forwarding state of the matching address to no store-forwarding and rejecting the load request.

Abstract: A pipelined microprocessor includes circuitry for store forwarding by performing: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one complete block of data; merging store data from the store request with the complete block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated complete block of data into a store data queue; for each load request, where the load request may require at least one updated completed block of data: determining if store forwarding is appropriate for the load request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the load request.

Abstract: A method and information processing system manage load and store operations that can be executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag, the load instruction becomes dependent upon all store instructions associated with a substantially similar hazard indicating flag.

Abstract: A method and system is provided that includes a controller that operates at least one piece of equipment according to setpoint values and a setpoint monitor in communication with the controller. The setpoint monitor receives setpoint modifications, each setpoint modification corresponding to a modification of one of the setpoint values. The setpoint monitor calculates an expected change in energy consumption of the at least one piece of equipment for each of the setpoint modifications and ranks the setpoint modifications based on the expected change in energy consumption. A first terminal is in communication with the setpoint monitor and displays the setpoint modifications in an order based on the ranking of the setpoint modifications. The first terminal receives input for each setpoint modification of the plurality of setpoint modifications indicating approval or rejection of the setpoint modification.

Abstract: An equipment storage soffit assembly comprises a base and a blocker door which is movable relative to the base between a closed state and a transit state. In the closed state the door cooperates with the base to form a storage space bounded at its bottom by the base and at its front by at least a portion of the blocker door. In the transit state the door is displaced from its closed state to accommodate transit of equipment between a stored position and a deployed position. The stored and deployed positions are on sides of the door that are opposite to each other when the door is in the closed state.

Abstract: A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

Abstract: A method and system is provided that includes receiving a current setpoint value from a controller that operates at least one piece of equipment according to the current setpoint value, the current setpoint value being set by a first user, comparing the current setpoint value with a benchmark setpoint value, and outputting the current setpoint value and the benchmark setpoint value on a terminal when the current setpoint value is different than the benchmark setpoint value. The method and system also includes receiving, with the terminal, input from a second user indicating one of approval of the current setpoint value or rejection of the current setpoint value, notifying the first user that the current setpoint value has been rejected when the input from the second user indicates rejection of the current setpoint value, and communicating, to the terminal, input from the first user indicating one of agreement or disagreement with the rejection of the current setpoint value.

Abstract: A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

Abstract: A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.

Abstract: A system and method for ultrasonic examination of a threaded test object, and more particularly, the mounting threads of a compressed gas tube while the tube is affixed to a tube trailer is provided. The disclosed ultrasonic test instrument includes a probe having one or more transducers for transmission and reception of ultrasound pulses, a contoured wear plate, and a shoe of highly attentuative material having a thread-like exterior surface adapted to mate with the threaded surface of the test object. The shoe further includes a narrow window in the thread-like exterior surface such that the shoe absorbs most of the ultrasonic pulses transmitted from the piezoelectric crystal except for the ultrasonic transmissions passing through the narrow window to the test object.

Abstract: Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.

Abstract: A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

Abstract: A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.