Patents by Inventor James R. Morgan

James R. Morgan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180368647
    Abstract: A wiping product is disclosed that is well suited for wiping up oils and greases. More particularly, the wiping product has been engineered to wipe up and absorb oils within the interior of the product. The wiper is made from a laminate containing outer layers designed to wick away and/or adsorb oily substances from a surface. The wiper also includes an elastic middle layer that is oil absorbable. In one embodiment, the outer layers are stretch bonded to the elastic middle layer so that the outer layers gather and create void spaces within the product.
    Type: Application
    Filed: July 29, 2016
    Publication date: December 27, 2018
    Inventors: Yu-Wen Chang, John Gavin MacDonald, Vikram S. Kaul, Jennifer L. Doherty, James R. Morgan, Kaiyuan Yang, Michael R. Vaughan
  • Patent number: 6809396
    Abstract: An integrated circuit (100) includes high performance complementary bipolar NPN and PNP vertical transistors (10, 20). The NPN transistor is formed on a semiconductor substrate whose surface (24) is doped to form a PNP base region (28, 70). A film (32, 34, 30) is formed on the surface with an opening (42) over an edge of the base region. A first conductive spacer (48) is formed along a first sidewall (78) of the opening to define a PNP emitter region (67) within the base region. A second conductive spacer (47) is formed along a second sidewall (76) of the opening to define a PNP collector region (66).
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: October 26, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Peter J. Zdebel, Misbahul Azam, Gary H. Loechelt, James R. Morgan, Julio C. Costa
  • Publication number: 20040099896
    Abstract: An integrated circuit (100) includes high performance complementary bipolar NPN and PNP vertical transistors (10, 20). The NPN transistor is formed on a semiconductor substrate whose surface (24) is doped to form a PNP base region (28, 70). A film (32, 34, 30) is formed on the surface with an opening (42) over an edge of the base region. A first conductive spacer (48) is formed along a first sidewall (78) of the opening to define a PNP emitter region (67) within the base region. A second conductive spacer (47) is formed along a second sidewall (76) of the opening to define a PNP collector region (66).
    Type: Application
    Filed: November 25, 2002
    Publication date: May 27, 2004
    Applicant: Semiconductor Components Industries, LLC.
    Inventors: Peter J. Zdebel, Misbahul Azam, Gary H. Loechelt, James R. Morgan, Julio C. Costa
  • Patent number: 5099796
    Abstract: The system includes a cage which has at least two wall portions with an open lattice structure and with a plurality of flexible rope sections joined to one another at their first ends and connected to the cage itself at their second ends by connecting mechanisms. Joining mechanisms may be included for joining the first ends of said flexible rope sections. In another embodiment, the sytem of the present invention involves a cage with at least two wall portions of open lattice structure and at least one multiple perch-creating flexible rope. The rope has a first end and a second end with separate connecting mechanisms on each end and the flexible rope is connected at one end to a first location of the cage and is then woven in a back and forth manner to create a plurality of perch sections within the cage and, finally, the second end with the connecting mechanism is attached to yet a different location within the cage.
    Type: Grant
    Filed: May 23, 1991
    Date of Patent: March 31, 1992
    Inventor: James R. Morgan