Patents by Inventor James R. Murdock

James R. Murdock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5927942
    Abstract: A shroud segment for a gas turbine engine includes a rail engaged with adjacent support structure to retain the segment and to provide sealing between the segment and the adjacent structure. Various construction details are disclosed which provide an effective sealing and retaining feature that permits differing thermal growth between the segment and the support structure. In a particular embodiment, a shroud segment includes a rail along a forward edge. The rail is engaged with a recess in the support structure to retain the segment and with a band which positions the segment and seals the forward edge.
    Type: Grant
    Filed: October 27, 1993
    Date of Patent: July 27, 1999
    Assignee: United Technologies Corporation
    Inventors: Matthew Stahl, Daniel E. Kane, James R. Murdock, Donald E. Haddad
  • Patent number: 4646299
    Abstract: A plurality of test signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative amplitude of the response signal with respect to a programmed reference level. The digitally programmed source is included for providing gated voltage-current crossover forcing functions during functional testing to minimize the disturbance when the device being tested is connected and to protect out of tolerance devices. Programmable voltage and current values define a pass window to assure a non-ambiguous go/no-go result during testing.
    Type: Grant
    Filed: May 17, 1984
    Date of Patent: February 24, 1987
    Assignee: Fairchild Semiconductor Corporation
    Inventors: John Schinabeck, James R. Murdock
  • Patent number: 4635259
    Abstract: A plurality of test signal applying and response signal monitoring circuits is coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and response signal monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative magnitude of the response signal with respect to a programmed reference level on a repetitive basis during testing to increase test rate. Other features are also disclosed.
    Type: Grant
    Filed: May 17, 1984
    Date of Patent: January 6, 1987
    Assignee: Fairchild Semiconductor Corporation
    Inventors: John Schinabeck, James R. Murdock