Patents by Inventor James R. Neal

James R. Neal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6594556
    Abstract: An apparatus for regulating voltage and power in a computer system is disclosed. The voltage and power regulation is performed by voltage regulation circuitry on a voltage regulator module. The voltage regulator module is a detachable unit which interfaces with the motherboard through a socket connector. The socket connector has a fixed pin definition which allows a variety of voltage regulator modules programmed to regulate voltages and power at different levels to be implemented on the motherboard.
    Type: Grant
    Filed: February 5, 1997
    Date of Patent: July 15, 2003
    Assignee: Intel Corporation
    Inventors: Louis W. Agatstein, James R. Neal
  • Patent number: 6006447
    Abstract: The present invention discloses a device for a shoe insole having multiple layers which form an air circulation system. A first layer is a fabric-like covering; a non-deformable second and deformable third layers forming together a layer with a cavity therein having offset apertures therein communicating by means of the cavity positioned underneath the fabric-like covering; a fourth layer made of foam rubber like material that deflates under the user's weight and re-expands when not under the user's weight; a bottom layer being a stiffer layer that forms a recess for receiving the other layers. A first and second exhaust conduit is formed in a side extension area for outward passage of stale air. The layers are joined to each other and the device is then inserted into the shoe of the user. The weight of the user is alternatively placed on and removed from the insole while walking or running. When the weight of the user is on the insole it compresses and stale air is forced out the exhaust conduit.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: December 28, 1999
    Inventors: James R. Neal, Estella B. Lindsay
  • Patent number: 5967161
    Abstract: A foldable umbrella fan is constructed of a form-retaining pleated shield and a protective support binder. The pleated shield of the umbrella fan may be fanned open 360.degree. into a full circle for use as an umbrella. Alternatively, the pleated shield may be fanned partially open for use as a fan. The pleated shield also may be fully collapsed to store the closed umbrella fan in a briefcase, handbag, or pocket.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: October 19, 1999
    Inventor: James R. Neal
  • Patent number: 5946470
    Abstract: An upgrade integrated circuit is used in a board without redesigning the board. The board is operative at a first voltage level, and the upgrade integrated circuit is operative at a second voltage level. The method comprises the steps of intercepting a first set of signals originating from the board. These signals are shifted using a voltage level shifter to be operative at a second voltage level. The voltage level shifter, however, does not reside on the board. The voltage level shifted signals are provided to the upgrade integrated circuit. The upgrade integrated circuit and the voltage level shifter may reside on a processor card.
    Type: Grant
    Filed: May 15, 1996
    Date of Patent: August 31, 1999
    Assignee: Intel Corporation
    Inventors: James R. Neal, Ted W. Pickerrell, Jr., Louis W. Agatstein, Jr.
  • Patent number: 5621245
    Abstract: A very large scale integrated (VLSI) chip designed to operate at 3.3 volts is modified to be compatible with prior systems having a 5 volt voltage supply. A central processing unit (CPU) is fabricated at a center position on an integrated circuit chip that has an operating voltage of 3.3 volts. The chip is soldered into a pin grid array (PGA) package and a heat sink is attached on the PGA package above the CPU. A 5 volt-to-3.3 volt voltage regulator having a 5 volt input and a 3.3 volt output is placed at an edge of the PGA package. The 3.3 volt output of the voltage regulator is connected to the 3.3 volt operating voltage input of the chip. The VCC 5 V on board pins are connected to the 5 volt input of the voltage regulator and the 3.3 volt output of the voltage regulator is connected to the VCC pins of the chip. VSS ground on board pins are connected in common to both the ground terminal of the voltage regulator and the VSS pads of the chip.
    Type: Grant
    Filed: October 31, 1996
    Date of Patent: April 15, 1997
    Assignee: Intel Corporation
    Inventors: Willy Agatstein, Mostafa Aghazadeh, Chia-pin Chiu, Amar Ghori, James R. Neal, Gregory Turturio
  • Patent number: 5556811
    Abstract: A very large scale integrated (VLSI) chip designed to operate at 3.3 volts is modified to be compatible with prior systems having a 5 volt voltage supply. A central processing unit (CPU) is fabricated at a center position on an integrated circuit chip that has an operating voltage of 3.3 volts. The chip is soldered into a pin grid array (PGA) package and a heat sink is attached on the PGA package above the CPU. A 5 volt- to- 3.3 volt voltage regulator having a 5 volt input and a 3.3 volt output is placed at an edge of the PGA package. The 3.3 volt output of the voltage regulator is connected to the 3.3 volt operating voltage input of the chip. The VCC 5V on board pins are connected to the 5 volt input of the voltage regulator and the 3.3 volt output of the voltage regulator is connected to the VCC pins of the chip.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: September 17, 1996
    Assignee: Intel Corporation
    Inventors: Willy Agatstein, Mostafa Aghazadeh, Chia-pin Chiu, Amar Ghori, James R. Neal, Gregory Turturio
  • Patent number: 5483102
    Abstract: A circuit and method for reducing an internal clocking frequency of the semiconductor device upon receiving a first signal indicating that a fan element disposed on the semiconductor device is operating at an unacceptable performance level and/or a second signal indicating that the semiconductor device is operating at a temperature greater than a prescribed boundary temperature.
    Type: Grant
    Filed: May 12, 1994
    Date of Patent: January 9, 1996
    Assignee: Intel Corporation
    Inventors: James R. Neal, Peter F. Brown, Louis W. Agatstein, Michael Gutman