Patents by Inventor James R. Reinders

James R. Reinders has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6698011
    Abstract: A method and system of transforming a source code file to obtain a reduced size source code file. In one embodiment, a source code file is translated to obtain a translation error list. The source code file is transformed to obtain a reduced size source code file, which is a test case file that is equivalent to the source code file. In one embodiment, a source code file is translated to obtain a translation error list and a reduced size source code file is automatically translated to obtain a reduced size source code file translation error list. The error lists are compared in order to determine whether the reduced size source code file is an equivalent test case for the source code file.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: February 24, 2004
    Assignee: Intel Corporation
    Inventors: James R. Reinders, Joe H. Wolf, III, Matthew E. Frazer
  • Publication number: 20030061022
    Abstract: A method to display a language translation includes displaying a word of a first language on an information display and displaying a first translation of the word of the first language into a second language proximate to the word of the first language. A second translation of the word of the first language into the second language may be displayed beneath the first translation of the word of the first language. The first translation of the word is displayed in a first color, which is different from a color used to display the word.
    Type: Application
    Filed: September 21, 2001
    Publication date: March 27, 2003
    Inventor: James R. Reinders
  • Patent number: 5819088
    Abstract: Improved parallelism in the generated schedules of basic blocks of a program being compiled is advantageously achieved by providing an improved scheduler to the code generator of a compiler targeting a multi-issue architecture computer. The improved scheduler implements the prior-art list scheduling technique with a number of improvements including differentiation of instructions into squeezed and non-squeezed instructions, employing priority functions that factor in the squeezed and non-squeezed instruction distinction for selecting a candidate instruction, tracking only the resources utilized by the non-squeezed instructions, and tracking the scheduling of the squeezed and non-squeezed instructions separately. When software pipelining is additionally employed to further increase parallelism in program loops, the improved scheduler factors only the non-squeezed instructions in the initial minimum schedule (initiation internal) size calculation.
    Type: Grant
    Filed: March 25, 1993
    Date of Patent: October 6, 1998
    Assignee: Intel Corporation
    Inventor: James R. Reinders