Abstract: An EEPROM programming circuit is disclosed which provides for the on-board rogramming of a EEPROM memory using:a microprocessor, a bootstrap ROM, a UART communications port, and a Eccles-Jordan flip flop switch system. These elements are electrically connected to a host system and the EEPROM by a central data bus. In normal operation, the host system sends a first set of data signals through the circuit to the EEPROM, which produces a set of processed signals. In operation in the programming mode the host system sends a second set of data signals to cause the microprocessor to send a switch signal to the Eccles-Jordan flip flop switch and to the bootstrap ROM. The bootstrap ROM contains the program code that forms the programs that are used to program the EEPROM.

Abstract: The speed at which a display screen is updated is increased by updating only those areas of the screen that have changed since the last update. This is accomplished by dividing the screen display elements into a grid of contiguous areas, and defining those areas which changing video information as unprotected areas and other areas as protected areas. As new images are generated, the memory containing information displayed in the protected areas is protected from updating while that in the unprotected area is not protected.

Abstract: A data storage device includes two registers associated with each cell of the memory. The first register forms a read/write memory register, and the second register forms a write-only shadow register connected to the memory register. During normal operations, each memory register operates as an independent random access memory (RAM) cell and each shadow register operates as an independent write-only RAM cell. When data is written to a shadow register, a flag bit is set. Subsequently, a validity check may be performed to verify the data. If the data does not verify, a clear line may be used to clear the flag bits. If the data verifies, the data in each shadow register with a flag bit set can be loaded into its corresponding memory register in a gang loading operation. If a shadow register flag bit is not set, the data in its corresponding memory register is not changed during gang loading.

Abstract: A timing circuit is disclosed for use with microprocessors which perform bit slicing within their arithmetic logic units. This timing circuit combines the synchronization of digital data inputs with the generation of the clocking signal, by dividing an oscillator frequency signal into the clocking signal, using a number of cycles of the oscillator frequency signal to synchronize the digital data inputs with the clocking signal, and outputting a synchronized clocking signal as soon as the digital data input signals are synchronized with the clocking signals. In a situation where the clock is derived by dividing the oscillator frequency by four, two of the four oscillator cycles are used to resynchronize the test input. The waste of overhead wait states and individual input resynchronization circuits are eliminated.

Abstract: A data driven clock generator provides a clock having a minimum cycle for a computer processor that implements asynchronous operations. The clock generator includes a basic oscillator that provides a feedback signal as a first input to a logic gate. A data valid signal, which may be generated by a multiplexer having a plurality of test inputs, is provided as a second input to the logic gate. The logic gate produces a trigger signal for starting the oscillator. If an asynchronous operation is not complete by the end of the minimum clock cycle, the oscillator is halted to stretch the clock until a data valid signal is received. The feedback signal provided to the logic gate guarantees completion of a minimum clock cycle upon receipt of a data valid signal even if the data valid signal is unstable during the clock cycle.

Abstract: A digital comparison system and technique enables an easy determination of the digital range within which digital addresses or data may fall or be selected. In one embodiment, the entire memory or addres space is divided into a predetermined number of sections, and each section's location in memory is defined by a predetermined first number of digits of the address. Likewise each address within a section is defined by a second predetermined number of digits of the address. A digital identifier is assigned to each section to define the position of a section with respect to a desired range. Digital identifiers are also assigned to each address within a section to fix the end points within each section. The outputs from memory devices storing the identifiers are coupled through a multiplexer which allows the position of a selected address to be identified as inside, outside, or an end point of a predetermined range.