Abstract: A probe tip structure that decreases the accumulation rate of Sn particles to the probe tip and enables considerably more efficient and complete laser cleaning is disclosed. In an embodiment, the probe structure includes an array of probe tips, each probe tip having an inner core; an interfacial layer bonded to the inner core; and an outer layer bonded to the interfacial layer, wherein the outer layer is resistant to adherence of the solder of the ball grid array package.

Abstract: A probe tip structure that decreases the accumulation rate of Sn particles to the probe tip and enables considerably more efficient and complete laser cleaning is disclosed. In an embodiment, the probe structure includes an array of probe tips, each probe tip having an inner core; an interfacial layer bonded to the inner core; and an outer layer bonded to the interfacial layer, wherein the outer layer is resistant to adherence of the solder of the ball grid array package.

Abstract: A probe tip structure that decreases the accumulation rate of Sn particles to the probe tip and enables considerably more efficient and complete laser cleaning is disclosed. In an embodiment, the probe structure includes an array of probe tips, each probe tip having an inner core; an interfacial layer bonded to the inner core; and an outer layer bonded to the interfacial layer, wherein the outer layer is resistant to adherence of the solder of the ball grid array package.

Abstract: A probe tip structure that decreases the accumulation rate of Sn particles to the probe tip and enables considerably more efficient and complete laser cleaning is disclosed. In an embodiment, the probe structure includes an array of probe tips, each probe tip having an inner core; an interfacial layer bonded to the inner core; and an outer layer bonded to the interfacial layer, wherein the outer layer is resistant to adherence of the solder of the ball grid array package.

Abstract: The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to “stain” a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process to facilitate the detection of a specific chip structure. Further, a specific chip structure is doped with a fluorescent material during the semiconductor process. A method of the present invention comprises: providing a first and a second material; processing the first material to form a portion of a semiconductor structure; and detecting a condition of the second material to determine whether processing of the first material is complete.

Abstract: Disclosed is a method of manufacturing integrated circuit chips that partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points. Once joined, the integrated circuit wafer is chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Then, after reducing the thickness of the integrated circuit wafer, the invention performs conventional processing on the integrated circuit wafer to form devices and wiring in the integrated circuit wafer. Next, the invention cuts through the integrated circuit wafer and the supporting wafer to form chip sections. During this cutting process, the integrated circuit wafer separates from the supporting wafer in chip sections where the integrated circuit wafer is not joined to the supporting wafer by the joining points.