Abstract: The prevention of the formation of undesired defects formed during the etching of etched metal interconnect lines on an integrated circuit during an integrated circuit manufacturing process that involves laying down on a semiconductor wafer a thin film such as an anti-reflective coating (ARC) on a layer of metal to be patterned into the metal interconnects of the individual integrated circuits. To do this the anti-reflective coating layer is covered with an oxide layer prior to applying and patterning subsequent photoresist. The specific metalization layer disclosed can be of aluminum, copper or copper-aluminum alloy. The ARC as disclosed is a nitride layer, such as titanium nitride. The oxide may be formed on the ARC in a number of known ways and may be etched subsequently alone or in combination with the underlying ARC and metal after subsequent photoresist deposit upon the oxide layer.

Abstract: A method for manufacturing integrated circuits increases the aspect ratio of the electrical conductor members connected to the circuits by increasing the effective height of the conductors, either by forming a thicker layer of conductor material prior to patterning the conductor members, or by adding a capping dielectric layer to the conductor material prior to patterning, or by overetching the dielectric material underlying the conductor members.The structure is then covered by a dielectric layer having poor step coverage, resulting in a number of voids and open spaces in the dielectric layer to thereby reduce the dielectric constant between the patterned conductors. A plasma etchback of the dielectric layer is employed to open and shape additional voids and open spaces in the dielectric layer. This is followed by the deposition of a second layer of dielectric material to seal the structure, including any open spaces in the first layer of dielectric material.