Abstract: The invention provides an improved differential output structure with minimal skew and introduces less process variations. According to one embodiment of the invention, a differential output structure is provided and comprises an input line, an output driver and a sync circuit. The input line includes first and second paths. The first path has an input end for receiving input signals. The first path also has an output end and includes at least one driving element. The second path has an input end operably coupled to the input end of the first path for receiving the input signals. The second path also has an output end. The output driver is operably coupled to the output ends of the first and second paths and is configured to provide differential outputs. The sync circuit is operably coupled between the first and second paths and is configured to synchronize the speed of signals traveling on the two paths.

Abstract: The invention provides an improved differential output structure with minimal skew and introduces less process variations. According to one embodiment of the invention, a differential output structure is provided and comprises an input line, an output driver and a sync circuit. The input line includes first and second paths. The first path has an input end for receiving input signals. The first path also has an output end and includes at least one driving element. The second path has an input end operably coupled to the input end of the first path for receiving the input signals. The second path also has an output end. The output driver is operably coupled to the output ends of the first and second paths and is configured to provide differential outputs. The sync circuit is operably coupled between the first and second paths and is configured to synchronize the speed of signals traveling on the two paths.

Abstract: The invention provides an improved differential output structure with minimal skew and introduces less process variations. According to one embodiment of the invention, a differential output structure is provided and comprises an input line, an output driver and a sync circuit. The input line includes first and second paths. The first path has an input end for receiving input signals. The first path also has an output end and includes at least one driving element. The second path has an input end operably coupled to the input end of the first path for receiving the input signals. The second path also has an output end. The output driver is operably coupled to the output ends of the first and second paths and is configured to provide differential outputs. The sync circuit is operably coupled between the first and second paths and is configured to synchronize the speed of signals traveling on the two paths.

Abstract: The invention provides a way of protecting a differential pair of transistors by providing a current path between input terminals of the transistors, while limiting the voltage across reversed biased junctions of the transistors. The invention also allows a larger swing of input voltage at the input terminals of the transistors. According to the present invention, an electrostatic discharge protection circuit is provided for protecting a differential pair of transistors. Each transistor includes first and second terminals and an input terminal. The second terminals of the transistors are connected to each other. The circuit comprises a pair of bypassing circuits and a clamping circuit. Each bypassing circuit is connected in parallel with a junction formed by the input and second terminals of an associated one of the transistors to limit a voltage across the junction when the junction is reverse biased.

Abstract: The invention provides an improved differential output structure with minimal skew and introduces less process variations. According to one embodiment of the invention, a differential output structure is provided and comprises an input line, an output driver and a sync circuit. The input line includes first and second paths. The first path has an input end for receiving input signals. The first path also has an output end and includes at least one driving element. The second path has an input end operably coupled to the input end of the first path for receiving the input signals. The second path also has an output end. The output driver is operably coupled to the output ends of the first and second paths and is configured to provide differential outputs. The sync circuit is operably coupled between the first and second paths and is configured to synchronize the speed of signals traveling on the two paths.

Abstract: The invention provides a way of protecting a differential pair of transistors by providing a current path between input terminals of the transistors, while limiting the voltage across reversed biased junctions of the transistors. The invention also allows a larger swing of input voltage at the input terminals of the transistors. According to the present invention, an electrostatic discharge protection circuit is provided for protecting a differential pair of transistors. Each transistor includes first and second terminals and an input terminal. The second terminals of the transistors are connected to each other. The circuit comprises a pair of bypassing circuits and a clamping circuit. Each bypassing circuit is connected in parallel with a junction formed by the input and second terminals of an associated one of the transistors to limit a voltage across the junction when the junction is reverse biased.

Abstract: A circuit arrangement provides a way of protecting a differential pair of bipolar transistors by diverting the current into an n-channel MOSFET which is driven into conduction during an ESD event and allows a larger swing of input voltage than the anti-parallel diode pair. No extra processing steps are required and the MOSFET is driven on, rather than relying on parasitic bipolar npn transistor triggering into snap-back as in the grounded gate NMOS transistor that is commonly used for ESD protection in CMOS integrated circuits. An ESD protection circuit is provided for protecting a differential pair of transistors having two input terminals.

Abstract: The invention provides a way of protecting a differential pair of bipolar transistors by diverting the current into an n-channel MOSFET which is driven into conduction during an ESD event and allows a larger swing of input voltage than the anti-parallel diode pair. No extra processing steps are required and the MOSFET is driven on, rather than relying on parasitic bipolar npn transistor triggering into snap-back as in the grounded gate NMOS transistor that is commonly used for ESD protection in CMOS integrated circuits. According to the present invention, an ESD protection circuit is provided for protecting a differential pair of transistors having two input terminals.