Abstract: The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (110) having a gate corner (125). The transistor (100) also includes a drain-extended well (115) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The drain-extended well (115) also has a low-doped region (145) between high-doped regions (150), wherein an edge of the low-doped region (155) is substantially coincident with a perimeter (140) defined by the gate corner (125). Other embodiments of the present invention include a method of manufacturing a transistor (200) and an integrated circuit (300).

Abstract: The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (110) having a gate corner (125). The transistor (100) also includes a drain-extended well (115) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The drain-extended well (115) also has a low-doped region (145) between high-doped regions (150), wherein an edge of the low-doped region (155) is substantially coincident with a perimeter (140) defined by the gate corner (125). Other embodiments of the present invention include a method of manufacturing a transistor (200) and an integrated circuit (300).

Abstract: The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (110) having a gate corner (125). The transistor (100) also includes a drain-extended well (115) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The drain-extended well (115) also has a low-doped region (145) between high-doped regions (150), wherein an edge of the low-doped region (155) is substantially coincident with a perimeter (140) defined by the gate corner (125). Other embodiments of the present invention include a method of manufacturing a transistor (200) and an integrated circuit (300).

Abstract: A semiconductor device (102) that includes a drain extended PMOS transistor (CT1a) is provided, as well as fabrication methods (202) therefore. In forming the PMOS transistor, a drain (124) of the transistor is formed over a region (125) of a p-type upper epitaxial layer (106), where the region (125) of the p-type upper epitaxial layer (106) is sandwiched between a left P-WELL region (130a) and a right P-WELL region (130b) formed within the p-type upper epitaxial layer (106). The p-type upper epitaxial layer (106) is formed over a semiconductor body (104) that has an n-buried layer (108) formed therein. This arrangement serves to increase the breakdown voltage (BVdss) of the drain extended PMOS transistor.

Abstract: Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

Abstract: A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, 78) underneath the source (94) and drain regions (96) and spanning the gap between the P-well gate (90F) and adjacent P-well isolation regions (46, 50).

Abstract: Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with p and n type dopants to facilitate depletion operation at Vgs=0, and an adjust region is implanted in the substrate proximate the channel side end of the thick gate dielectric structure for improved breakdown voltage rating. The compensated channel region is formed by overlapping implants for an n-well and a p-well, and the adjust region is formed using a Vt adjust implant with a mask exposing the adjust region.

Abstract: A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, 78) underneath the source (94) and drain regions (96) and spanning the gap between the P-well gate (90F) and adjacent P-well isolation regions (46, 50).

Abstract: Methods and apparatus are disclosed for fabricating thick and thin gate oxide transistors in a semiconductor device, wherein lightly doped source/drain regions for the thick gate oxide transistors are formed using a threshold voltage adjust implant, and lightly doped source/drain regions for the thin gate oxide transistors are formed using an LDD implant. The use of threshold voltage implantation to form the lightly doped source/drain regions for the thick gate oxide transistors allows lower dopant concentrations therein compared with the thin gate oxide transistors without the need for separate LDD implantation processing for transistors of different gate oxide thicknesses.

Abstract: Methods and apparatus are disclosed for fabricating thick and thin gate oxide transistors in a semiconductor device, wherein lightly doped source/drain regions for the thick gate oxide transistors are formed using a threshold voltage adjust implant, and lightly doped source/drain regions for the thin gate oxide transistors are formed using an LDD implant. The use of threshold voltage implantation to form the lightly doped source/drain regions for the thick gate oxide transistors allows lower dopant concentrations therein compared with the thin gate oxide transistors without the need for separate LDD implantation processing for transistors of different gate oxide thicknesses.

Abstract: The present invention relates to an NMOS transistor structure which comprises a p-well region in a semiconductor substrate, an n-type source region in the p-well region, and an n-type drain region in the p-well region. The source and drain regions are laterally spaced apart from one another and define a p-type channel region therebetween in the p-well region. The NMOS transistor further comprises a gate having a gate electrode and a gate oxide overlying the channel region of the p-well region. A PDUF region underlies the p-well region and exhibits a resistivity which is less than the p-well region, wherein the PDUF region lowers a resistance associated with the p-well region at high drain voltages. The lowered resistance decreases a gain associated with a parasitic bipolar transistor and increases an injection induced breakdown voltage characteristic of the NMOS transistor structure.

Abstract: An electronic circuit (20), comprising a semiconductor substrate (22) and a first layer (30) in a fixed physical relation to the semiconductor substrate. The electronic circuit further comprises a well (32a) formed in the first layer, wherein the well comprises a first conductivity type and has a side dimension and a bottom dimension. The electronic circuit further comprises a first enclosure (34, 26) surrounding the side dimension and the bottom dimension of the well, wherein the first enclosure comprises a second conductivity type complementary of the first conductivity type and has a side dimension and a bottom dimension. The electronic circuit further comprises a second enclosure (32b, 24) surrounding the side dimension and the bottom dimension of the first enclosure, wherein the second enclosure comprises the first conductivity type.

Abstract: A semiconductor device (10) is provided that comprises a substrate (12) having a first conductivity type. An epitaxial layer (14) of a second conductivity type is formed outwardly from the substrate (12). An isolation region (16) is formed in the epitaxial layer (14) and the substrate (12). A guard ring (18) is formed in portions of the substrate (12) and portions of the epitaxial layer (14). An active region (20) of the second conductivity type is defined in the epitaxial layer (14) by the isolation region (16) and the guard ring (18). A gate body (24, 26) is insulatively disposed outwardly from the active region (20). An insulative structure (32) having a plurality of contact openings (34) and (36) is disposed outwardly from the gate body (24, 26) and the epitaxial layer (14). A conductive interconnect layer (38) is disposed outwardly from the insulative structure (32) and fills the contact openings (34) and (36).

Abstract: A method for fabricating a self-aligned DMOS transistor is provided. The method includes forming a passivation layer (18, 68) on an oxide layer (16, 66) of a substrate (12, 56). The oxide layer (16, 66) is then removed from the surface of the substrate (12, 56) where it is exposed through the passivation layer (18, 68). A reduced surface field region (36, 74) is then formed where the surface of the substrate (12, 56) is exposed through the passivation layer (18, 68). An oxide layer (38, 80) is then formed on the reduced surface field region (36, 74).

Abstract: A high current power transistor is provided that comprises a drain region that includes a highly-doped drain region (54) and a lightly-doped drain region (50). The channel region (52) is activated by a gate conductor (32). The channel region separates the lightly-doped drain region (50) from a D-well region (40). A sidewall insulator body (44) is used to form the lightly-doped drain region (50) and the lightly-doped drain region (54). The transistor is formed in an active region (20) which comprises a portion of an n-type epitaxial layer (12) formed outwardly from a p-type substrate (10). The isolation structures (14) and (16) as well as the epitaxial layer (12) provides for a transistor that can be used in both source follower and common source configurations.

Abstract: A Schottky diode circuit 20 is formed on a semiconductor layer 24. A conductive contact 36 on the surface of the semiconductor layer 24 forms a Schottky barrier 40 at the junction of the conductive contact 36 and the semiconductor layer 24. A guard ring 26 in the semiconductor layer 24 is adjacent to the Schottky barrier 40 and is separated from the conductive contact 36 by a portion of the semiconductor layer 24. No direct electrical path exists between the guard ring 26 and the conductive contact 36.

Abstract: A Schottky diode circuit 20 is formed on a semiconductor layer 24. A conductive contact 36 on the surface of the semiconductor layer 24 forms a Schottky barrier 40 at the junction of the conductive contact 36 and the semiconductor layer 24. A guard ring 26 in the semiconductor layer 24 is adjacent to the Schottky barrier 40 and is separated from the conductive contact 36 by a portion of the semiconductor layer 24. No direct electrical path exists between the guard ring 26 and the conductive contact 36.

Abstract: An integrated process is shown for the fabrication of one or more of the following devices: (n-) and (p-) channel low-voltage field-effect logic transistors (139/140); (n-) and (p-) channel high-voltage insulated-gate field-effect transistors (141, 142) for the gating of an EEPROM memory array or the like; a Fowler-Nordheim tunneling EEPROM cell (143); (n-) and (p-) channel drain-extended insulated-gate field-effect transistors (144, 145); vertical and lateral annular DMOS transistors (146, 147); a Schottky diode (148); and a FAMOS EPROM cell (149). A "non-stack" double-level poly EEPROM cell (676) with enhanced reliability (676) is also disclosed.

Abstract: A field effect transistor (147) is formed in a region of a second semiconductor layer (171), having a first conductivity type. A tank region (196) of a second conductivity type opposite the first conductivity type is formed in the semiconductor region (171), and defines a tank area on the face of the semiconductor layer (171). A first highly doped region (276) formed to be of the first conductivity type is formed within the region (171) and to be spaced from the tank region (196). A gate insulator layer (218) is formed on at least one selected portion of the face, this selected portion including a portion of the tank area (196). A conductive gate (246) is formed on the gate insulator layer over the selected portion of the face. At least one second highly doped region (278) is formed at the face within the tank area to be of the first conductivity type, and to have at least one lateral edge self-aligned to a corresponding one of the lateral edges of the gate (246 ).

Abstract: Methods and circuits of integrated DMOS, CMOS, NPN, and PNP devices include self-aligned DMOS (411) with increased breakdown voltage and ruggedness for recovery from transients including additional Zener diodes (402/474).