Patents by Inventor James R. Torossian
James R. Torossian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10409935Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: GrantFiled: April 11, 2016Date of Patent: September 10, 2019Assignee: Synopsys, Inc.Inventors: Neville A. Clark, James R. Torossian
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Patent number: 10360327Abstract: A method or apparatus for transforming a provided virtual processor model to a user virtual processor model. The method in on embodiment comprises transforming a virtual processor model to simulate a user target processor, by receiving a transformable virtual processor model having a transformable instruction set and a transformable pipeline, and transforming the transformable virtual processor model to a user virtual processor model designed to simulate a user target processor.Type: GrantFiled: June 16, 2015Date of Patent: July 23, 2019Assignee: Synopsys, Inc.Inventors: Neville A. Clark, James R. Torossian
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Publication number: 20190095547Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: ApplicationFiled: April 11, 2016Publication date: March 28, 2019Inventors: Neville A. Clark, James R. Torossian
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Publication number: 20170293702Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: ApplicationFiled: April 11, 2016Publication date: October 12, 2017Inventors: Neville A. Clark, James R. Torossian
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Patent number: 9311437Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: GrantFiled: February 3, 2014Date of Patent: April 12, 2016Assignee: Synopsys, Inc.Inventors: Neville A. Clark, James R. Torossian
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Publication number: 20150310150Abstract: A method or apparatus for transforming a provided virtual processor model to a user virtual processor model. The method in on embodiment comprises transforming a virtual processor model to simulate a user target processor, by receiving a transformable virtual processor model having a transformable instruction set and a transformable pipeline, and transforming the transformable virtual processor model to a user virtual processor model designed to simulate a user target processor.Type: ApplicationFiled: June 16, 2015Publication date: October 29, 2015Inventors: Neville A. Clark, James R. Torossian
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Patent number: 9058447Abstract: A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.Type: GrantFiled: June 10, 2013Date of Patent: June 16, 2015Assignee: Synopsys, Inc.Inventors: Neville A. Clark, James R. Torossian
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Publication number: 20140156249Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: ApplicationFiled: February 3, 2014Publication date: June 5, 2014Applicant: Synopsys, Inc.Inventors: Neville A. Clark, James R. Torossian
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Patent number: 8644305Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: GrantFiled: January 22, 2008Date of Patent: February 4, 2014Assignee: Synopsys Inc.Inventors: Neville A. Clark, James R. Torossian
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Publication number: 20130282358Abstract: A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.Type: ApplicationFiled: June 10, 2013Publication date: October 24, 2013Inventors: Neville A. Clark, James R. Torossian
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Patent number: 8463589Abstract: A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.Type: GrantFiled: July 30, 2007Date of Patent: June 11, 2013Assignee: Synopsys, Inc.Inventors: Neville A. Clark, James R. Torossian
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Patent number: 7567893Abstract: A simulation system, a computer product to implement a simulation method, and a method of simulating a digital circuit that has at least one element and at least one clock signal having clock attributes. The method includes maintaining a data structure for time-scheduled events scheduled to occur at particular simulation-times; and maintaining a data structure for clock-scheduled events each corresponding to a particular clock signal and scheduled to occur at a time that can be determined from at least one attribute of the clock signal, such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure.Type: GrantFiled: December 20, 2005Date of Patent: July 28, 2009Assignee: VaST Systems Technology CorporationInventors: James R. Torossian, Neville A. Clark
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Publication number: 20080319730Abstract: A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.Type: ApplicationFiled: July 30, 2007Publication date: December 25, 2008Applicant: VAST SYSTEMS TECHNOLOGY CORPORATIONInventors: Neville A. Clark, James R. Torossian
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Publication number: 20080235415Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: ApplicationFiled: January 22, 2008Publication date: September 25, 2008Applicant: VaST Systems Technology CorporationInventors: Neville A. CLARK, James R. Torossian
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Hardware and software co-simulation including simulating a target processor using binary translation
Patent number: 6751583Abstract: A co-simulation design system to simulate on a host an electronic system that includes target digital circuitry and a target processor with an accompanying user program. The system includes a processor simulator to simulate execution of the user program by executing host software that includes an analyzed version of the user program. The system further includes a hardware simulator to simulate the target digital circuitry and an interface mechanism that couples the hardware simulator with the processor simulator. The user program is provided in binary form. Determining the analyzed version of the user program includes decomposing the user program into linear blocks, translating each linear block of the user program into host code that simulate the operations of the linear block, storing the host code of each linear block in a host code buffer for the linear block, and adding timing information into the code in the host code buffer on the time it would take for the target processor to execute the user program.Type: GrantFiled: August 20, 2001Date of Patent: June 15, 2004Assignee: VaST Systems Technology CorporationInventors: Neville A. Clarke, James R. Torossian -
Patent number: 6584436Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.Type: GrantFiled: March 27, 2001Date of Patent: June 24, 2003Assignee: Vast Systems Technology, Inc.Inventors: Graham R. Hellestrand, Ricky L. K. Chan, Ming Chi Kam, James R. Torossian
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Publication number: 20020032559Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.Type: ApplicationFiled: March 27, 2001Publication date: March 14, 2002Inventors: Graham R. Hellestrand, Ricky L.K. Chan, Ming Chi Kam, James R. Torossian
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Publication number: 20020019969Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via an interface mechanism. The execution of a user program on a target processor that includes a cache is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator. The analysis also adds hooks to the user program such that executing the analyzed user program on the host computer system invokes a cache simulator that simulates operation of the cache.Type: ApplicationFiled: May 9, 2001Publication date: February 14, 2002Inventors: Graham R. Hellestrand, King Yin Cheung, James R. Torossian, Ricky L.k. Chan, Ming Chi Kam, Foo Ngok Yong
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Patent number: 6263302Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via an interface mechanism. The execution of a user program on a target processor that includes a cache is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator. The analysis also adds hooks to the user program such that executing the analyzed user program on the host computer system invokes a cache simulator that simulates operation of the cache.Type: GrantFiled: January 26, 2000Date of Patent: July 17, 2001Assignee: Vast Systems Technology CorporationInventors: Graham R. Hellestrand, King Yin Cheung, James R. Torossian, Ricky L. K. Chan, Ming Chi Kam, Foo Ngok Yong
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Patent number: 6230114Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.Type: GrantFiled: October 29, 1999Date of Patent: May 8, 2001Assignee: Vast Systems Technology CorporationInventors: Graham R. Hellestrand, Ricky L. K. Chan, Ming Chi Kam, James R. Torossian