Abstract: An apparatus and method for testing an access time of a macro embedded in a LSI chip. The apparatus includes a logical gate connected to the output latches of the macro, thereby controlling the access time of the macro, and a test latch for determining an on-chip delay time between a test signal for enabling the output latches and an input signal for enabling the macro. The method includes the steps of determining the on-chip delay time between the test signal and the input signal, thereby allowing the test signal to be synchronized with the input signal, supplying the synchronized test signal to the output latches for a manufacturer specified macro access time, and testing the latched output data from the macro.

Abstract: A memory array device with an embedded self-test binary pattern. The device has an array of bistable cells formed with first and second sides that are oppositely connected to a first voltage line or a second voltage line. If the first and second voltage lines are energized at the same voltage level, each of the bistable cells will function in a normal bistable mode. If the first and second voltage lines are energized at different levels, each of the bistable cells will function in an embedded binary pattern mode.