Abstract: A method and apparatus for detection and correction of errors in binary coded information. The method involves receiving a word of binary coded information and grouping the bits of the word of information. Parity bits are generated for each of the groups of bits. The bits are grouped according to three rules: (1) for any three parity bits, there is either one data bit or no data bit whose value effects all three parity bits, (2) for any four parity bits, there is no data bit whose value effects all four, and (3) for any data bit, there are exactly three parity bits whose values are effected by its value. The word bits and parity bits are stored on memory circuits. The bits are stored on the memory circuits in accordance with three rules: (1) no memory circuit may have both data bits and parity bits stored on it, (2) for all bits on a data chip, the sets of parity bits affected by them intersect in one parity bit, (3) for all parity chips, no data bit effects the value of three bits on the chip.

Abstract: A physical cache unit (100) is used within a computer (20). The computer (20) further includes a main memory (99) a memory control unit (22), inputs/output processors (54, 68) and a central processor (156). The central processor includes an address translation unit (118), an instruction processing unit (126), an address scalar unit (142), a vector control unit (144) and vector processing units (148, 150). The physical cache unit (100) stores operands in a data cache (180), the operands for delivery to and receipt from the control processor (156). Addresses for requested operands are received from the central processor (156) and are examined concurrently during one clock cycle in tag stores (190 and 192). The tag stores (190 and 192) produce tags which are compared in comparators (198 and 200) to the tag of physical addresses received from the central processor (156).

Abstract: A vector processing computer (20) includes a memory control unit (22), main memory (99), a central processor (156), a service processing unit (42) and a plurality of input/output processors (54, 68). The central processor (156) includes a physical cache unit (100), an address translation unit (118), an instruction processing unit (126), an address scalar unit (142), a vector control unit (144), an odd pipe vector processing unit (148) and an even pipe vector processing unit (150). Vector elements are transmitted from memory, either main memory (99), a physical cache unit (100) or a logical cache (326) through a source bus (114) where the elements are alternately loaded into the vector processing units (148, 150). The resulting vectors are transmitted through a destination bus (114) to either the physical cache unit (100), the main memory (99), the logical cache (326) or to an input/output processor (54).

Abstract: The computer (10) includes a memory control unit (12), a central processing unit (14) and a memory array unit (16). A plurality of memory array planes (36, 38, 40 and 42) are included within the memory array unit (16). A latch (82) receives write data from the memory control unit (12) through a bus (26). Address and control information is transferred from the memory control unit (12) to timing and address circuits (28, 30, 32, 34). The write data is transferred from the latch (82) into a selected one of the memory array planes (36, 38, 40, 42). For each of the memory array planes (36, 38, 40, 42) there is provided a respective read latch (60, 62, 64, 66) for receiving read data. The ouputs of the memory array planes are not connected in common. The ouputs to read latches (60, 62, 64,66) are connected in common through a bus (76) for transferring read data through the data bus (26) back to the memory control unit (12).

Abstract: A memory array unit (20) is used within a main memory (26) of a computer system (10). The memory (26) comprises a plurality of memory array units (20, 22, 24) and each of the memory array units (20, 22, 24) has an allocated address range of 0 to 16 megabytes. However, the memory array unit (20) has a capacity of only four megabytes. The usable address range is 0 to 2 megabytes and 8 to 10 megabytes. The remainder of the address range is a null. Upon development of an increased memory array unit (20) having a greater capacity, such as 16 megabytes, the new memory array unit (20) is directly substituted for the previous low capacity memory array unit. The new memory array unit (20) has a fully implemented address range from 0 to 16 megabytes. The low and high capacity memory array units can be intermixed or the low capacity units can be entirely replaced by the high capacity units without the need for modifying any of the computer system (10) or for modifying the system software.

Abstract: A read/modify/write circuit (10) for a computer is used in conjunction with a main memory (12) in which block operations are executed using a plurality of data units. The circuit (10) includes a first register connected to receive a data block from the main memory (12), a second register connected to receive data units from a requestor, such as a processor (18) and a third register in which a resulting data block is produced which comprises the data units to be written into the main memory (12) and the remaining data units which were previously in the block read from memory (12). Multiplex circuits (70, 72, 74, 76, 78, 80, 82 and 84) are commanded by a decoder (136) in response to the processor (18) to selectively route sections of registers (26 and 28) into a register (106). The resulting data block is then transferred through the memory bus (14) for writing into the main memory (12).

Abstract: A physical cache unit (100) is used within a computer (20). The computer (20) further includes a main memory (99) a memory control unit (22), inputs/output processors (54, 68) and a central processor (156). The central processor includes an address translation unit (118), an instruction processing unit (126), an address scalar unit (142), a vector control unit (144) and vector processing units (148, 150). The physical cache unit (100) stores operands in a data cache (180), the operands for delivery to and receipt from the control processor (156). Addresses for requested operands are received from the central processor (156) and are examined concurrently during one clock cycle in tag stores (190 and 192). The tag stores (190 and 192) produce tags which are compared in comparators (198 and 200) to the tag of physical addresses received from the central processor (156).

Abstract: A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor.