Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.

Abstract: A circuitized substrate having plated through-holes wherein the plated through-holes are, tented with a polyimide material is provided along with the process for fabricating such.

Abstract: A substrate having enhanced mechanical rigidity and including high stiffness reinforcing layers, a conductive layer and non-cloth dielectric layers wherein the non-cloth dielectric layers have a modulus of elasticity which is less than the modulus of elasticity of the reinforcing layers and of the conductive layer. The high stiffness reinforcing layers are disposed off the neutral axis and away from the center of the organic substrate to increase the flexural rigidity and flexural yield strength of the organic substrate.

Abstract: A method of making a flip chip package that maintains flatness over a wide temperature range and provides good heat dissipation is described. A laminate substrate is electrically connected to electrical contacts disposed on a chip and underfill material is applied between the soldered connections. A body, for example an uncured dielectric material, is applied to the chip, the laminate substrate, a thermally conductive member or combinations thereof, and thermally conductive member is disposed adjacent to the surface of the chip that is opposite the surface connected to the laminate substrate. The body is extruded between the chip and the thermally conductive member. The thickness of the thermally conductive member is determined by balancing the stiffness and the CTE of both the thermally conductive member and the laminate substrate, and the length and width of the thermally conductive member may vary but are at least the size of the corresponding length and width of the chip.

Abstract: A method is provided for connecting two conductive surfaces in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive surface, applying a dielectric insulation material over the first conductive surface such that the dendrites are exposed through the insulation material to leave a substantially planar surface of exposed dendrites, and placing a second conductive surface on top of the exposed dendrites. The second conductive surface may be a surface metal, a chip bump array, or a ball grid array. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection and planarization manufactured in accordance with the present invention.

Abstract: A substrate for connecting one element having a first coefficient of thermal expansion to another element having a differing coefficient of thermal expansion that will alleviate interconnection problems due to thermal mismatch.

Abstract: A method of making a multilayered circuit board wherein at least two layered subassemblies, each comprising a dielectric layer and at least one conductive layer therein, are bonded together. Each subassembly includes a through-hole extending therethrough which is aligned with a respective through-hole of the other prior to bonding. The subassemblies are compressed at a predetermined pressure (e.g., 300 psi) and then heated to a first temperature (e.g., 300.degree. C.) for an established time period, resulting in formation of a bond between the two through-holes. The resulting alloy formed from this bond possesses a melting point significantly greater than that of the subassembly dielectric (e.g., PTFE). Following this time period, the compressed subassemblies are heated to an even greater temperature (e.g., 380.degree. C.), again for an established time period, to assure dielectric flow. The subassembly is then cooled and the pressure removed.

Abstract: A method of making a multilayered circuit board wherein at least two layered subassemblies, each comprising a dielectric layer and at least one conductive layer therein, are bonded together. Each subassembly includes a through-hole extending therethrough which is aligned with a respective through-hole of the other prior to bonding. The subassemblies are compressed at a predetermined pressure (e.g., 300 psi) and then heated to a first temperature (e.g., 300.degree. C.) for an established time period, resulting in formation of a bond between the two through-holes. The resulting alloy formed from this bond possesses a melting point significantly greater than that of the subassembly dielectric (e.g., PTFE). Following this time period, the compressed subassemblies are heated to an even greater temperature (e.g., 380.degree. C.), again for an established time period, to assure dielectric flow. The subassembly is then cooled and the pressure removed.

Abstract: Two metallic surfaces are bonded together by coating each of the metallic surfaces with a layer of a first material and a layer of a second and different material contacting the layer of the first material. The first material and second material are chosen so that a eutectic liquid layer will form at the interface between them. The layers of the second material on each of the metallic surfaces are abutted together and then the layers are heated above the eutectic temperatures to form a localized liquid, which upon solidification results in an interconnection between the surfaces.