Patents by Inventor James Rachana Bou

James Rachana Bou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10056893
    Abstract: A power module has a lead frame, a first power chip, a second power chip, a plurality of single in-line leads, a gate drive and protection integrated circuit (IC), a plurality of bonding wires and a molding encapsulation. The first and second power chips are attached to a top surface of the lead frame. The plurality of single in-line leads has a high voltage power lead, a low voltage power lead and a plurality of signal control leads. The low voltage power lead has a lead portion and an extension portion. The gate drive and protection IC is attached to the extension portion of the low voltage power lead. The molding encapsulation encloses the first and second power chips, the extension portion of the low voltage power lead, the gate drive and protection IC, the plurality of bonding wires and at least a majority portion of the lead frame.
    Type: Grant
    Filed: October 16, 2016
    Date of Patent: August 21, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Bum-Seok Suh, Zhiqiang Niu, Wonjin Cho, Son Tran, James Rachana Bou
  • Publication number: 20180109249
    Abstract: A power module has a lead frame, a first power chip, a second power chip, a plurality of single in-line leads, a gate drive and protection integrated circuit (IC), a plurality of bonding wires and a molding encapsulation. The first and second power chips are attached to a top surface of the lead frame. The plurality of single in-line leads has a high voltage power lead, a low voltage power lead and a plurality of signal control leads. The low voltage power lead has a lead portion and an extension portion. The gate drive and protection IC is attached to the extension portion of the low voltage power lead. The molding encapsulation encloses the first and second power chips, the extension portion of the low voltage power lead, the gate drive and protection IC, the plurality of bonding wires and at least a majority portion of the lead frame.
    Type: Application
    Filed: October 16, 2016
    Publication date: April 19, 2018
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Bum-Seok Suh, Zhiqiang Niu, Wonjin Cho, Son Tran, James Rachana Bou
  • Patent number: 9881856
    Abstract: An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth transistors, a tie bar, a low voltage IC, a high voltage IC, a first, second and third boost diodes, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die paddle. The second transistor is attached to the second die paddle. The third transistor is attached to the third die paddle. The fourth, fifth and sixth transistor s are attached to the fourth die paddle. The low and high voltage ICs are attached to the tie bar. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth transistors, the tie bar, the low and high voltage ICs, and the first, second and third boost diodes. The IPM has a reduced top surface area and a reduced number of leads compared to a conventional IPM.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: January 30, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Bum-Seok Suh, Zhiqiang Niu, Wonjin Cho, Cheow Khoon Oh, Son Tran, James Rachana Bou
  • Patent number: 9704789
    Abstract: An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth transistors, a tie bar, a low voltage IC, a high voltage IC, a first, second and third boost diodes, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die paddle. The second transistor is attached to the second die paddle. The third transistor is attached to the third die paddle. The fourth, fifth and sixth transistor s are attached to the fourth die paddle. The low and high voltage ICs are attached to the tie bar. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth transistors, the tie bar, the low and high voltage ICs, and the first, second and third boost diodes. The IPM has a reduced top surface area and a reduced number of leads compared to a conventional IPM.
    Type: Grant
    Filed: October 16, 2016
    Date of Patent: July 11, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Bum-Seok Suh, Zhiqiang Niu, Wonjin Cho, Cheow Khoon Oh, Son Tran, James Rachana Bou