Abstract: A chip former for directing material cut from a workpiece. The chip former having a body with a top side, a bottom side, a front side, and a back side. The front side consists of a surface forming a wall with a section of the surface having a concave geometry configured to direct material that comes off a workpiece. A method for directing material cut from a workpiece.

Abstract: A double block valve and a valve proving system are disclosed. The double block valve is actuated by a single actuator and includes a valve body housing a cavity. The cavity defines an upstream portion with a fluid inlet and a downstream portion with a fluid outlet. A seating assembly is interposed between the upstream and the downstream portions. A first and a second blocking element are disposed in the valve body and are both movable within the cavity between opened and closed positions. With the first and second blocking elements both contacting the seating assembly, the space therebetween defines an enclosed space with a finite volume. The proving system is used for two safety shut-off valves on a valve train, such as a double block valve. The proving system connects to an enclosed space established between the two safety shut-off valves and includes a pair of three-way valves, oppositely biased pressure switches, and a pump, all of which are interconnected through pneumatic conduits.

Abstract: A method, system, and apparatus for placing and removing data elements into a bi-directionally growing first in last out data structure is provided. In one embodiment, in response to a request to place a data element into the data structure, a head pointer is advanced one memory location in a direction indicated by a state of a direction flag. The new data element is placed into the memory location indicated by the head pointer. The position of the head pointer and the base pointer are swapped in preparation for receiving a new data element and the state of the direction flag is reversed to indicate growth of the data structure in the opposite direction. In response to a request to remove a data element from the data structure, the head and base pointers are swapped and the state of the direction flag is reversed.

Abstract: A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified.

Abstract: A double block valve and a valve proving system are disclosed. The double block valve is actuated by a single actuator and includes a valve body housing a cavity. The cavity defines an upstream portion with a fluid inlet and a downstream portion with a fluid outlet. A seating assembly is interposed between the upstream and the downstream portions. A first and a second blocking element are disposed in the valve body and are both movable within the cavity between opened and closed positions. With the first and second blocking elements both contacting the seating assembly, the space therebetween defines an enclosed space with a finite volume. The proving system is used for two safety shut-off valves on a valve train, such as a double block valve. The proving system connects to an enclosed space established between the two safety shut-off valves and includes a pair of three-way valves, oppositely biased pressure switches, and a pump, all of which are interconnected through pneumatic conduits.

Abstract: A method and apparatus for dynamically driving events in a simulation of a data processing system are implemented. Events, or system states, are generated by drivers located at predetermined locations within the simulation model under test. These events, which are drawn from a predetermined class of events, termed “effects,” are driven in response to other events observed by monitors disposed within the simulation model in accordance with a predetermined set of “causes,” and a set of “rules” that map causes to effects. The driving of events is mediated by a library process that receives observed events from the monitors, in the form of data structures, stored them in a database, and passes the effects to be driven to the appropriate driver in accordance with the set of rules, also data structures stored in the database, when a cause corresponds to a observed event.

Abstract: A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified.

Abstract: One aspect of the invention relates to a method for detecting architectural violations in a multiprocessor computer system. In one version of the invention, the method includes the steps of generating a testcase instruction stream having a plurality of instructions, executable by the processors, which access a memory which is shared by the processors; detecting dependent instructions in the testcase instruction stream; and modifying the testcase instruction stream by inserting logging instructions in the testcase in the testcase instruction stream which cause data associated with observable instructions to be written to a logging memory by writing a first sequence of unique monotonically increasing values to the memory.

Abstract: A multiprocessor data processing system includes a shared main memory and a plurality of processors connected to the memory utilizing a system bus. Data is transferred utilizing the system bus. The plurality of processors include a first processor and a second processor. The first processor includes a first cache, and the second processor includes a second cache. The multiprocessor data processing system executes a test program. During execution of the test program, a first and a second trace are generated. The first trace is generated by monitoring all events occurring at a first location within the system. The second trace is generated by monitoring all events occurring at a second location within the system. Each event is associated with a time of occurrence of that event. The first trace includes each event which was monitored at the first location and the time associated with each event.

Abstract: One aspect of the invention relates to a method for detecting synchronization violations in a multiprocessor computer system having a memory location which controls access to a portion of memory shared by the processors, the memory location having at least one lock bit indicating whether the portion of memory is locked by one of the processors and a plurality of bits for storing a data value. The method comprises reading the memory location by an individual processor; testing the lock bit to determine whether the portion of memory is locked; if the portion of memory is not locked; asserting the lock bit to indicate the portion of memory is locked; incrementing the data value to represent a global access count; writing the lock bit and the data value back to the memory location; and incrementing a data value stored in a memory location associated with the individual processor to indicate an individual access count by the individual processor.