Patents by Inventor James Ray Bailey

James Ray Bailey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160282408
    Abstract: A system including an embedded logic analyzer block having an input receiving a plurality of signals from a system under test, and a trigger event block detecting an occurrence of an event based in part upon the plurality of signals. The system further includes a block with a first input receiving one or more of the plurality of signals, a second input receiving a signal based upon the detection of the occurrence of the event, circuitry generating a distinct set test signals based on the signals at the first input and second input of the block, the distinct set of test signals being different from the plurality of signals appearing at the input of the embedded logic analyzer block, and an output providing the generated distinct set of test signals to the embedded logic analyzer block as additional test signals for at least one of sampling thereof and event triggering.
    Type: Application
    Filed: June 8, 2016
    Publication date: September 29, 2016
    Inventors: Eric David Langevin, James Patrick Sharpe, James Ray Bailey
  • Patent number: 9405651
    Abstract: A computer implemented method includes receiving a log file with a textual description of the operation of a system. The textual description is converted to event waveforms, where each event waveform has a time axis and event indicia. A representation of the event waveforms is supplied.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: August 2, 2016
    Assignee: Initial State Technologies, Inc.
    Inventor: James Ray Bailey
  • Patent number: 9405755
    Abstract: A method implemented by a computer includes receiving a log file with log file data characterizing the operation of a system. A normalized format for the log file data is proposed. User input on the normalized format is solicited. The normalized format is set. The log file data is converted to the normalized format. A visualization application operative with the normalized format is selected. The visualization application supplies visualizations of the log file data.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: August 2, 2016
    Assignee: Initial State Technologies, Inc.
    Inventors: James Ray Bailey, David Leo Sulpy, Adam Matthew Reeves
  • Patent number: 9405610
    Abstract: A computer implemented method includes receiving a data stream from a client device. The data stream includes a textual description of the operation of a system. The textual description includes at least one textual instruction. The textual description is converted to event waveforms where each event waveform has a time axis and event indicia. The textual instruction is rendered as an ideogram associated with the event waveforms. A representation of the event waveforms and the ideogram is supplied.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 2, 2016
    Assignee: Initial State Technologies, Inc.
    Inventors: James Ray Bailey, Adam Matthew Reeves
  • Publication number: 20160011953
    Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.
    Type: Application
    Filed: November 19, 2014
    Publication date: January 14, 2016
    Inventor: James Ray Bailey
  • Patent number: 9170901
    Abstract: A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: October 27, 2015
    Assignee: Lexmark International, Inc.
    Inventors: James Ray Bailey, Christopher W Case, James Patrick Sharpe, James Alan Ward, Michael Anthony Marra, III
  • Patent number: 8914681
    Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: December 16, 2014
    Assignee: Lexmark International, Inc.
    Inventor: James Ray Bailey
  • Patent number: 8745447
    Abstract: A system for testing or debugging a system including the integrated circuit having an embedded logic analyzer. In one embodiment, the system includes a computing device coupled to the logic analyzer for receiving the at least one output. A user interface run on the computing device assigns an attribute to at least one signal associated with the logic analyzer, determines a new signal or value not provided by the logic analyzer, the new signal or value being based upon the at least one signal as received from the logic analyzer and upon a predetermined definition, and presents the new signal or value to a system user.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: June 3, 2014
    Assignee: Lexmark International, Inc.
    Inventors: James Ray Bailey, Christopher W. Case, Michael Anthony Marra, III
  • Patent number: 8516304
    Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefore. In one embodiment, an integrated circuit includes a logic analyzer having a first input receiving a plurality of signals and an output for providing an indication of a detection, by the logic analyzer, of at least one trigger event; and a built in self test block having a first input for receiving one or more of the signals appearing at the first input of the logic analyzer, a second input coupled to the output of the logic analyzer for selectively enabling the BIST block, the BIST block generating and maintaining a signature based upon the first and second inputs thereof.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: August 20, 2013
    Assignee: Lexmark International, Inc.
    Inventors: James Ray Bailey, Christopher Wilson Case, James Patrick Sharpe
  • Patent number: 8210631
    Abstract: Disclosed is a method for printing a media sheet in a media processing device. The method includes aligning a first portion of a printhead of the media processing device to a print area of the media sheet. The method further includes printing the print area of the media sheet by traversing the printhead over the print area in a first direction. The printing is performed by the first portion. Further, the method includes aligning a second portion of the printhead to the print area by adjusting the media sheet relative to the printhead by an index distance in a direction perpendicular to the first direction. Thereafter, the method includes reprinting the print area by traversing the printhead over the print area in a second direction opposite to the first direction. The reprinting is performed by the second portion.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: July 3, 2012
    Assignee: Lexmark International, Inc.
    Inventors: James Ray Bailey, Lucas David Barkley, John Booth Bates, James Lesesne Bush, III, Michael Anthony Marra, III
  • Publication number: 20120144256
    Abstract: A system for testing or debugging a device under test having an embedded logic analyzer. In one embodiment, the system includes software stored in non-transitory memory for testing a device under test having an embedded logic analyzer, the software program product having instructions which, when executed by a computing device associated with the device under test cause the computing device to reconstruct signals of interest in the device under test based at least in part upon signals captured by the embedded logic analyzer during the test or debug session, and cause the computing device to display the reconstructed signals of interest to a user of the computing device.
    Type: Application
    Filed: November 30, 2011
    Publication date: June 7, 2012
    Inventors: James Ray Bailey, Christopher W. Case, James Patrick Sharpe, James Alan Ward, Michael Anthony Marra, III
  • Patent number: 8103712
    Abstract: A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the approximate quotient; c) determining a quotient adjustment value based on the initial error; d) determining whether to apply the quotient adjustment value to the approximate quotient; e) if the determination at d) is YES, then applying the quotient adjustment value to the approximate quotient; f) determining an iterative error of the approximate quotient; g) updating the quotient adjustment value based on the iterative error; h) repeating acts d) through g) until the determination at d) is NO, thereby determining a final value for the approximate quotient; i) generating an integer quotient based on the final value of the approximate quotient; and j) using the integer quotient with regard to at least one aspect of the system.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: January 24, 2012
    Assignee: Lexmark International, Inc.
    Inventors: James Ray Bailey, Zachary Nathan Fister, Jimmy Daniel Moore, Jr.
  • Publication number: 20110167311
    Abstract: A system for testing or debugging a system including the integrated circuit having an embedded logic analyzer. In one embodiment, the system includes a computing device coupled to the logic analyzer for receiving the at least one output. A user interface run on the computing device assigns an attribute to at least one signal associated with the logic analyzer, determines a new signal or value not provided by the logic analyzer, the new signal or value being based upon the at least one signal as received from the logic analyzer and upon a predetermined definition, and presents the new signal or value to a system user.
    Type: Application
    Filed: December 31, 2010
    Publication date: July 7, 2011
    Inventors: James Ray Bailey, Christopher W. Case, Michael Anthony Marra, III
  • Publication number: 20110047424
    Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.
    Type: Application
    Filed: August 18, 2009
    Publication date: February 24, 2011
    Inventors: James Ray Bailey, James Alan Ward
  • Publication number: 20110047427
    Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment, an integrated circuit includes a logic analyzer having a first input receiving a plurality of signals and an output for providing an indication of a detection, by the logic analyzer, of at least one trigger event; and a built in self test block having a first input for receiving one or more of the signals appearing at the first input of the logic analyzer, a second input coupled to the output of the logic analyzer for selectively enabling the BIST block, the BIST block generating and maintaining a signature based upon the first and second inputs thereof.
    Type: Application
    Filed: September 8, 2010
    Publication date: February 24, 2011
    Inventors: James Ray Bailey, Christopher Wilson Case, James Patrick Sharpe
  • Publication number: 20110047423
    Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.
    Type: Application
    Filed: September 8, 2010
    Publication date: February 24, 2011
    Inventor: James Ray Bailey
  • Publication number: 20100309489
    Abstract: A method for printing of raster data in a media processing device is disclosed. The method includes identifying an attribute of a set of raster lines of the raster data. The method further includes determining at least one print mode from a plurality of print modes based on the attribute. Each print mode of the plurality of print modes is configured to print the set of raster lines of the raster data. Furthermore, the method includes printing the set of raster lines of the raster data in the at least one print mode.
    Type: Application
    Filed: June 9, 2009
    Publication date: December 9, 2010
    Inventors: James Ray Bailey, Lucas David Barkley, John Booth Bates, James Lesesne Bush, III, Eric David Langevin, Michael Anthony Marra, III
  • Patent number: 7821687
    Abstract: A method for dynamically compensating for a faulty pixel in a scan line of a scanner having an image sensor with a plurality of sensor pixels includes generating digitized scan data; processing the digitized scan data to compensate for any faulty pixels of the plurality of sensor pixels to form compensated scan data; processing the compensated scan data to apply offset and gain correction to the compensated scan data to form calibrated scan data; processing the calibrated scan data to adjust the calibrated scan data to compensate for human visual perception to form final scan data; and storing the final scan data in a scanner image memory.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: October 26, 2010
    Assignee: Lexmark International, Inc.
    Inventors: James Ray Bailey, David Allen Crutchfield
  • Publication number: 20100245430
    Abstract: Disclosed is a method for printing a media sheet in a media processing device. The method includes aligning a first portion of a printhead of the media processing device to a print area of the media sheet. The method further includes printing the print area of the media sheet by traversing the printhead over the print area in a first direction. The printing is performed by the first portion. Further, the method includes aligning a second portion of the printhead to the print area by adjusting the media sheet relative to the printhead by an index distance in a direction perpendicular to the first direction. Thereafter, the method includes reprinting the print area by traversing the printhead over the print area in a second direction opposite to the first direction. The reprinting is performed by the second portion.
    Type: Application
    Filed: March 25, 2009
    Publication date: September 30, 2010
    Inventors: James Ray Bailey, Lucas David Barkley, John Booth Bates, James Leseseme Bush, III, Michael Anthony Marra, III
  • Publication number: 20100091333
    Abstract: A method and an imaging apparatus for reducing print grain effect in an image to be printed by a printing device are disclosed. One or more flat field areas, each comprising at least one flat field pixel, are detected in the image. A color value of each detected flat field pixel in the one or more flat field areas is modified using a unique flat field optimized color lookup table. The modification of the color value of each flat field pixel in the image reduces the print grain effect in the image to be printed by the printing device.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 15, 2010
    Inventor: James Ray Bailey