Abstract: One example discloses a power management circuit, including: an ultrasonic transmitter configured to generate an ultrasonic signal having a set of transmitted ultrasonic signal attributes; an ultrasonic receiver configured to detect the ultrasonic signal having a set of received ultrasonic signal attributes; wherein the power management circuit is configured to cause a device to be operated at a first power level and a second power level; and a proximity detection circuit configured to transition the device from the first power level to the second power level in response to a preselected difference between the transmitted set of ultrasonic signal attributes and the received set of ultrasonic signal attributes.

Abstract: One example discloses a power management circuit, including: an ultrasonic transmitter configured to generate an ultrasonic signal having a set of transmitted ultrasonic signal attributes; an ultrasonic receiver configured to detect the ultrasonic signal having a set of received ultrasonic signal attributes; wherein the power management circuit is configured to cause a device to be operated at a first power level and a second power level; and a proximity detection circuit configured to transition the device from the first power level to the second power level in response to a preselected difference between the transmitted set of ultrasonic signal attributes and the received set of ultrasonic signal attributes.

Abstract: An electric field sensor including a dielectric layer having a plane surface, at least one transceiver antenna disposed on one side of the dielectric layer, the at least one transceiver antenna configured to emit a wave above the plane surface of the dielectric layer and detect an event adjacent the plane surface, an integrated circuit coupled to the at least one transceiver antenna.

Abstract: A wafer-level chip-scale package (WLCSP) includes an integrated circuit (IC) chip, and die bonding pads with a redistribution layer (RDL) having multiple via structures located directly below the footprint of a solder ball placed on the bonding pad. The via structures electrically connect the solder ball to a top metal layer of the IC chip. The RDL may extend beyond the solder ball's footprint and have additional vias that connect to the top metal layer, including vias located under and connected to other solder balls. The bonding pads have a low R-on resistance and are not susceptible to thermal-induced cracking.

Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.

Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.

Abstract: A switching circuit employs MEMS devices. In connection with various example embodiments, signal switching circuit couples primary and secondary data link connectors having at least two channels and an electrode for each channel. A MEMS switch is coupled to each channel in of the secondary data link connectors, and includes a suspended membrane, first and second contact electrodes (one being in the membrane) and a biasing circuit that biases the membrane for moving the membrane between open and closed positions to contact the electrodes. A switch controller circuit selectively controls the application of an actuation voltage to each of the biasing circuits, thereby selectively actuating the membranes between the open and closed positions for routing signals between the primary and secondary data link connectors.

Abstract: A switching circuit employs switches operating at low on resistance and high off capacitance. In connection with various example embodiments, a switching circuit selectively couples a communication port to one of two or more internal circuits based upon a type of input at the communication port. A sensor circuit senses the type of the input and, based upon the sensed input type, actuates one or more switches in the switching circuit.

Abstract: Bus communications are effected. In accordance with one or more example embodiments, a bus circuit is configured for communicating data in accordance with a main protocol (e.g., as a default), and for communicating with an alternate protocol when signals corresponding to the main protocol are not present. In some implementations, a sense circuit is used with input pins to sense a type of signal for bus communications, and to control communications on the bus with a protocol appropriate for the sensed signals, and for a main protocol when main protocol signals are sensed (e.g., for a default bus operation, or for test operation).

Abstract: Bus communications are effected. In accordance with one or more example embodiments, a bus circuit is configured for communicating data in accordance with a main protocol (e.g., as a default), and for communicating with an alternate protocol when signals corresponding to the main protocol are not present. In some implementations, a sense circuit is used with input pins to sense a type of signal for bus communications, and to control communications on the bus with a protocol appropriate for the sensed signals, and for a main protocol when main protocol signals are sensed (e.g., for a default bus operation, or for test operation).

Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.