Abstract: The present invention relates to a system and method for adjusting bit rate streaming during live video recording while traveling in a moving vehicle on public right-of-ways. The embodiments of the present invention relates to a system and method for gathering and analyzing dynamically and continuously cellular strength and bit loss while traveling from point A to point B. The result of the predictive bit rate is to adjust the video streaming throughput to best match the predictive bit rate and maximize the quality of the video stream.

Abstract: The present invention provides a number of advantageous modifications and improvements in wearable computing devices to optimize or at least more fully utilize the potential applications of such devices. These modifications include transforming the view of a second observer to be able to view what a first observer at a different location is viewing, allowing the second observer or a remote administrator to control the zoom on the device of a first observer, providing a pointer on the device of the first observer to assist in framing or viewing an object; and controlling the device to avoid overheating or to avoid transmitting redundant or hijacked information.

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue hat holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Abstract: A controller for a random access memory (RAM), such as a static ram (SRAM), includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues. The memory controller may be used in parallel processing systems and may also include an order queue, a lock lookup content addressable memory (CAM) and a read lock fail queue. A system including a media access controller (MAC), a network processor and an SRAM controller, and a method for controlling a RAM, are also described.

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of micro control functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Abstract: An audio channel system provides an analog signal corresponding to a sound waveform in a computer system. The audio channel system includes a plurality of audio channels. Each audio channel contains a predetermined number of audio data samples for producing a particular sound waveform. A plurality of volume bits define a volume level of each audio data sample to be played. An audio processor processes the sound waveforms of each audio channel. The audio processor acts as a shared processing element which receives the audio data samples from each audio channel. The audio processor divides the audio data samples into a plurality of data such that the plurality of data for each audio data sample is pipelined through the audio processor in a serial manner. The plurality of data for each audio data sample for each audio channel is in various processing stages at any given time.