Abstract: An integrated circuit including a circuit for improved efficiency of internal data transfer comprises: a processor core having a buffer memory; a random access memory having a read and write cycle time of a one clock cycle, the random access memory comprising a memory array with a predetermined word width and a data latch coupled to the memory array; a bi-directional data bus coupling the processor core to the random access memory, the bi-directional data bus having a data width which is a multiple of at least one times the predetermined word width; and, a signal circuit coupled to the data latch wherein the data latch is responsive to the signal circuit to latch data from the bi-directional data bus prior to writing the data to the memory array, wherein alternately reading two consecutive data words and writing two consecutive words occurs on an average in the clock cycle.