Patents by Inventor James Robert Wilcox
James Robert Wilcox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6570261Abstract: The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chin assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.Type: GrantFiled: April 8, 2002Date of Patent: May 27, 2003Assignee: International Business Machines CorporationInventors: Donald Seton Farquhar, Michael Joseph Klodowski, Konstantinos Papathomas, James Robert Wilcox
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Publication number: 20020111016Abstract: The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chin assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.Type: ApplicationFiled: April 8, 2002Publication date: August 15, 2002Applicant: International Business Machines CorporationInventors: Donald Seton Farquhar, Michael Joseph Klodowski, Konstantinos Papathomas, James Robert Wilcox
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Patent number: 6369449Abstract: The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chip assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.Type: GrantFiled: January 12, 1999Date of Patent: April 9, 2002Assignee: International Business Machines CorporationInventors: Donald Seton Farquhar, Michael Joseph Klodowski, Kostantinos Papathomas, James Robert Wilcox
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Publication number: 20010045637Abstract: The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chip assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.Type: ApplicationFiled: January 12, 1999Publication date: November 29, 2001Inventors: DONALD SETON FARQUHAR, MICHAEL JOSEPH KLODOWSKI, KOSTANTINOS PAPATHOMAS, JAMES ROBERT WILCOX
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Patent number: 6094059Abstract: A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head.Type: GrantFiled: February 1, 1999Date of Patent: July 25, 2000Assignee: International Business Machines CorporationInventors: Jerome A. Frankeny, Anthony P. Ingraham, James Steven Kamperman, James Robert Wilcox
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Patent number: 6094060Abstract: A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head.Type: GrantFiled: February 1, 1999Date of Patent: July 25, 2000Assignee: International Business Machines CorporationInventors: Jerome A. Frankeny, Anthony P. Ingraham, James Steven Kamperman, James Robert Wilcox
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Patent number: 5993579Abstract: A composite cable has a reinforcing layer with conductors disposed on opposed planar surfaces. Dielectric film layers electrically separate the conductors on the planar reinforcing layer from respective layers of additional conductors. The flexible cable is manufactured by laminating a layer of dielectric film and a layer of electrically conductive material onto both sides of a double clad core which provides a strain relief reinforcement for the cable.Type: GrantFiled: June 16, 1997Date of Patent: November 30, 1999Assignee: International Business Machines CorporationInventors: Donald Seton Farquhar, William Louis Brodsky, Natalie Barbara Feilchenfeld, Lisa Jeanine Jimarez, James Robert Wilcox
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Patent number: 5981312Abstract: The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chip assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.Type: GrantFiled: June 27, 1997Date of Patent: November 9, 1999Assignee: International Business Machines CorporationInventors: Donald Seton Farquhar, Michael Joseph Klodowski, Konstantinos Papathomas, James Robert Wilcox
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Patent number: 5949246Abstract: A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head.Type: GrantFiled: January 28, 1997Date of Patent: September 7, 1999Assignee: International Business MachinesInventors: Jerome A. Frankeny, Anthony P. Ingraham, James Steven Kamperman, James Robert Wilcox
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Patent number: 5942127Abstract: A fuel oil treatment unit and associated method for removing undesirable contaminants from a fuel oil, such as diesel oil, being delivered to an associated engine, such as a vehicle diesel engine. The invention includes, inter alia, a unit for treating contaminant-containing fuel oil, comprising means for heating the fuel oil to a temperature sufficient to volatilize at least some of the contaminants and, also, means for filtering the so-heated fuel oil, to remove therefrom at least some of the remaining, unvolatilized contaminants. Optionally, the previously-heated and filtered fuel oil is passed to a temperature control means for maintaining or returning the temperature of the fuel oil to a desired level.Type: GrantFiled: September 18, 1997Date of Patent: August 24, 1999Inventors: Steven Ian Wilcox, James Robert Wilcox
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Patent number: 5847324Abstract: A composite cable has a reinforcing layer with conductors disposed on opposed planar surfaces. Dielectric film layers electrically separate the conductors on the planar reinforcing layer from respective layers of additional conductors. The flexible cable is manufactured by laminating a layer of dielectric film and a layer of electrically conductive material onto both sides of a double clad core which provides a strain relief reinforcement for the cable.Type: GrantFiled: April 1, 1996Date of Patent: December 8, 1998Assignee: International Business Machines CorporationInventors: Donald Seton Farquhar, William Louis Brodsky, Natalie Barbara Feilchenfeld, Lisa Jeanine Jimarez, James Robert Wilcox
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Patent number: 5781413Abstract: A technique is disclosed for forming a chip cube from a plurality of chips laminated together in front-to-back relationship, the edges of the chip forming a cube face having a set of connectors for each chip thereon. A number "X" of functional chips is required for the operation, and "X+Y" is the number of chips provided in the stack such that there is Y number of chips greater than the number of functional chips required. If any number of chips equal to Y or less are found to be defective, there are enough chips remaining to perform the required function. Thereafter X number of good chips are connected to output circuitry through an interposer. Electrical connectors are provided on all of the IC chips. Contact pads for all of the connectors are provided on one face, and outlet pads are provided on the opposite face of the interposer for at least Y number of outlets. The interposer has vias at least equal to the number of outlet pads.Type: GrantFiled: September 30, 1996Date of Patent: July 14, 1998Assignee: International Business Machines CorporationInventors: Wayne John Howell, John Steven Kresge, David Brian Stone, James Robert Wilcox
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Patent number: 5736679Abstract: A novel through-hole interconnect for connecting a power plane conductor to a through-hole includes a central pad connected to the through-hole and a deformable hinge that connects the central pad with the power plane conductor in a multilayer circuit board. The central pad and hinge are defined by a non-continuous area removed from the plane conductor. Preferably this area has a C-shape. During the compression process to join the core assemblies, deformation of the hinge advantageously absorbs the shear forces and allows the power plane beyond the hinge to remain substantially planar. The resulting multilayer laminated circuit board includes a plurality of cores laminated together in a stacked configuration and a plurality of plated through-holes defined in said multilayer laminated circuit board each of which is connected to a plane conductor by a hinge deformed so that the interconnect area is aligned outside of a plane defined by the plane conductor.Type: GrantFiled: December 26, 1995Date of Patent: April 7, 1998Assignee: International Business Machines CorporationInventors: John Steven Kresge, David Noel Light, James Robert Wilcox
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Patent number: 5659951Abstract: A method for making a printed circuit board with a flush surface land begins by forming a multi-layer printed circuit board with a recess in a surface dielectric layer. Then, a hole is drilled into or through the printed circuit board; the hole communicates with the recess. After the recess is formed, a conductive material is provided in the recess to form a surface land and provided on an inner surface of the hole to form a plated hole which is electrically connected to the surface land. The conductive material in the recess has a thickness substantially equal to a depth of the recess such that the surface land is flush with an adjacent surface of the dielectric surface layer.Type: GrantFiled: April 15, 1996Date of Patent: August 26, 1997Assignee: International Business Machines CorporationInventors: Thomas Patrick Gall, David Brian Stone, Russell Thomas White, Jr., James Robert Wilcox