Abstract: A search coprocessor card for attachment to a computer system has an interface to a host processor of the computer system and a processor. The processor has memory for its program and data, and is coupled to one or more search engine devices. Each of the search engine devices is in turn coupled to a memory for holding key tables, and is capable of searching the key tables for matching entries.

Abstract: A digital demodulator (100) includes a differentiate and cross multiply stage (102) and a plurality of filter/decimator stages (106, 112, 118 and 108, 114, 120 and 110, 116, 122) that accept both multiple baud rates and multiple modulation deviation frequencies, and that provide a common frequency data stream at their respective outputs. One of said filter/decimator stages is coupled to a primary filter (124) which is followed by a box filter (134). The box filter (134) improves the overall filter response and provides notches at a specified frequency (e.g., 4800 Hz) and its harmonics. Demodulator (100) provides improved sensitivity without the need for any circuit trimming. The filter stages (e.g., 106, 112, 118; 108, 114, 120; and 110, 116, 122) used in demodulator (100) have been optimized to eliminate the need for costly multipliers.

Abstract: A method (900) and circuit (400) for automatic frequency correcting a frequency modulated (FM) digital signal determines a frequency offset value of the detected FM signal during a preamble portion of the FM digital signal, generates an offset corrected signal by removing the frequency offset value from a detected FM signal (440), and generates a frequency corrected signal (460). The frequency corrected signal is generated by selecting the offset corrected signal during the preamble portion, selecting the detected FM signal after the end of the preamble portion when a magnitude of the frequency offset value of the detected FM signal is below a predetermined threshold (445), and otherwise selecting the offset corrected signal after the end of the preamble portion.

Abstract: A selective call unit (800) comprising a receiver (100) and a processor (810) is used for decoding a 2-level radio signal. The processor (810) is adapted to convert in-phase and quadrature signals generated by the receiver (100) to a sequence of state transitions representative of the plurality of symbols. For each symbol in the plurality of symbols, the processor (810) counts the sequence of state transitions during a symbol period, and compares the recorded count to a predetermined threshold, thereby generating a comparison result. The processor (810) then calculates a bit decision threshold level based on an average of the comparison result for each symbol in the plurality of symbols. For each symbol in a plurality of subsequent symbols, the processor (810) then compares the bit decision threshold level to the sequence of state transitions counted during a symbol period to decode a digital logic level therefrom.