Abstract: A conduit support device may include a support leg that may be movably coupled to a boom arm with a vertical pivot and a horizontal pivot. The vertical pivot and horizontal pivot may be disposed between the distal end and the proximal end of the boom arm. An offset weight may be removably coupled to the boom arm. The offset weight may comprise a first end, a second end, and a center of balance, and the center of balance may be closer to the first end than to the second end. The first end may be configured to be positioned proximate to the boom arm to position the center of balance relatively closer to the boom arm, and the second end may be configured to be positioned proximate to the boom arm to position the center of balance relatively farther from the boom arm.

Abstract: A conduit support device may include a support leg that may be movably coupled to a boom arm with a vertical pivot and a horizontal pivot. The vertical pivot and horizontal pivot may be disposed between the distal end and the proximal end of the boom arm. An offset weight may be removably coupled to the boom arm. The offset weight may comprise a first end, a second end, and a center of balance, and the center of balance may be closer to the first end than to the second end. The first end may be configured to be positioned proximate to the boom arm to position the center of balance relatively closer to the boom arm, and the second end may be configured to be positioned proximate to the boom arm to position the center of balance relatively farther from the boom arm.

Abstract: A frequency monitoring system comprises a plurality of circuit cards. Each circuit card, such as a primary multiplexer card and a backup or redundant multiplexer card, has an oscillator that provides a reference clock signal. On each circuit card, a respective frequency compare element is configured to receive a clock signal to be measured and to provide a frequency error signal indicating a frequency error of the clock signal relative to an average frequency of a plurality of reference clock signals. Accordingly, the frequency measurements for the circuit cards are based on the same reference frequency (e.g., the average frequency of the reference clock signals from the oscillators).

Abstract: The present disclosure generally relates to pulse width modulation (PWM) clock and data receivers and methods for recovering data and timing information from received signals. A PWM clock and data receiver in one exemplary embodiment of the present disclosure has comparators for detecting pulses of a received data signal. The PWM clock and data receiver provides fixed frequency, variable duty cycle control signals that are used to control the biasing of the comparators to establish data decision levels for clock and data recovery. At times, the output of at least one comparator is used to perform peak detection, and the receiver controls the duty cycles of the control signals based on such peak detection in an effort to optimize the clock and data recovery process.

Abstract: A digital delay line-based, timing relationship detector is operative to generate a K+L bit digital output code representative of a timing/phase offset between first and second low frequency clock signals. A first digital code generator generates a K-bit most significant phase word based upon the number of high frequency clock signals counted between transitions in the two low frequency clock signals. A second digital code generator generates an L-bit least significant phase word based upon the effective length of a delay line/shift register, through which a digital value associated with a transition in one of the two clock signals propagates, until a transition of the next occurring high frequency clock signal. The contents of a counter are incrementally changed in accordance with the number of stages of the multistage digital delay line/shift register through which the digital value has propagated. The L-bit least significant phase word is defined in accordance with the contents of the counter.

Abstract: A high resolution digital phase-lock loop circuit is described, which is implemented with an input clock reference frequency which is approximately the same as the output frequency of the phase-lock loop. The output is derived from delaying the input clock a variable number of gate delays ranging from no delay to one period of the input clock. A shift register controls the number of gate delays and a 360 degree phase detector initializes the shift register when the output is delayed by one period of the input clock to provide no delay. Gate delay variations due to integrated circuit process, voltage and temperature are compensated for to provide a relatively constant clock phase correction.

Abstract: A center frequency high resolution digital phase-lock loop circuit (CF HRDPLL) is described with an input clock reference frequency which is equal to the output phase-locked frequency. The output is derived from delaying the input clock a variable number of gate delays ranging from no delay to one period of the input clock. A shift register controls the number of gate delays. A 360 degree phase detector initializes the shift register to provide no delay when the output is delayed by almost one period of the input clock and a phase retard correction occurs. An advance correction from a no delay condition causes a fast shift to occur to locate one period of delay while the output is held at no delay. The output is then switched to slightly less than one period of phase delay to allow further phase advance corrections to occur. Gate delay variations due to process, voltage and temperature are compensated for to provide a relatively constant clock phase correction.

Abstract: An automatic clock recovery circuit is described. The automatic clock recovery circuit samples a received data signal with a recovered clock signal and advances or retards the recovered clock signal based on the comparison between the received data signal and the recovered clock signal. The automatic clock recovery circuit selectively cancels advance or retard corrections in the presence of bias distortion and phase ambiguities to improve the lock acquisition time for recovered clock.

Abstract: An automatic bias control circuit for a data limiter in a synchronous data communications system is disclosed. After word synchronization is achieved, the automatic bias control circuit is enabled and a time relationship between the limited data signal edges and a synchronized local clock signal is detected. The automatically controlled bias level is then modified upward or downward by an additive or subtractive voltage increment for a period of time related to the data bit rate so that the true baseline of the data signal is approximated by the bias level and the detected time relationship is thereby adjusted so that the edges are essentially synchronized with the local clock signal.

Abstract: A circuit and technique for directing an adaptable antenna system is described. The invention is coupled to the output of an RF receiver configured to provide a data signal output, and evaluates the quality of the receiver data signal. The invention switches antennas when the signal quality deteriorates below a predetermined level.

Abstract: A programmable bias circuit for use with a data limiter circuit is described. The limiter and bias circuit are coupled to a portable data receiver which is adapted to communicate in a coded system. Frequency disparities between a transmitted word sync signal and the portable data terminal local oscillator signal will cause a DC offset voltage in the received data signal. The programmable bias circuit is controlled by a decoder within the portable data terminal. If the terminal is in an idle state, the programmable bias circuit will be set to rapidly follow offset voltage shifts until a transmitted word sync signal has been detected. After word sync has been detected, a slower, more stable time constant circuit is programmably activated for the duration of the digital data message. The fast time constant circuit is activated at the end of the received data signal.

Abstract: A system for distributing signals from an audio source to key telephone station instruments is disclosed. By controlling the impedance relationship between the station instruments, lines and amplifier output, cross-feeding of signals from one station instrument to another or back-feeding of signals to the audio source is prevented.

Abstract: A power converter which supplies AC or positive or negative DC output voltage with positive or negative current while isolating the output voltage from the input power source. This converter includes a pulse width modulator converts power amplitude signals to pulses of proportionate width. A power driver circuit applies these pulses to a sychronous demodulator and low pass filter via a pulse transformer. A low output impedance is presented to all output disturbances such that the converter can source or sink current in true four quadrant operation, including the passing of power from output to input when a load voltage exceeds the intended supply voltage.

Abstract: A protecting arrangement is dislcosed for multiple loads supplied from a single DC power source. Each load is monitored by a separate protection circuit. Detection of an over-current condition associated with one of the loads will cause the associated protection circuit to assume a non-conducting state and provide a visual indication of same. Periodically enabled common reset means are provided to restore conduction to non-conducting protection circuits following removal of the cause of over-current.