Abstract: A memory circuit (24) limits the threshold voltage distribution for either programming or erasing a memory cell (40A) in a non-volatile memory array (34). A data latch (90) provides a current (I.sub.REF) to the memory cell (40A) that increases in current as the operating temperature of the memory cells (40A, 40B) increases. Current generated by the data latch (90) increases when the processing parameters cause a greater conductivity of the transistors in the memory cell (40A) and the current decreases when the processing parameters cause a lesser conductivity of the transistors in the memory cell (40A), thus allowing narrower limits on the distribution of the program and erase threshold voltages.

Abstract: A charge pump (102) and method of charge pumping a low voltage (V.sub.DD)) to generate a higher voltage (V.sub.PP). A primary pump (160, 179, 180) receives complementary clock signals (CLK1, CLK2) that control charging and transfer cycles of the charge pump. During the charging cycle, a capacitor (150) stores a charge developed from the low voltage. On the transfer cycle, the charge is transferred to an output (138, 177, 178) through a switching transistor (152) disposed in a well region (202) to develop the higher voltage. A secondary pump (162, 187, 188) charge pumps the output voltage to generate a more positive bias voltage for biasing the well region to disable a parasitic PNP transistor of the switching transistor.

Abstract: A programming method for a floating gate memory circuit (100) includes a block erase (step 81) in which a first programming signal is applied to memory cells of a selected block of the memory to store a first value of charge in the memory cells of the block. Data is programmed by applying a second programming signal to a first memory cell to store a second value in the first memory cell (step 83). A third programming signal is applied to a second memory cell to write a correction charge that compensates for a change in the first value of charge induced by the second programming signal (step 84).

Abstract: A circuit (28) and method of sensing data stored in a memory circuit provide a reference current (I.sub.REF) that tracks memory cell current (I.sub.BIT) over a range of temperatures and power supply voltages. A comparator circuit (66) senses the memory cell current with respect to the reference current to produce the stored data (V.sub.DATA) By sensing current rather than voltage, the voltage swing on a high capacitance bitline (39) can be reduced to improve speed. The reference current is set during testing of the circuit by applying programming voltages (V.sub.WELL, V.sub.CG, V.sub.BL) to a reference device (52) that matches a storage device (36) in the memory cell (30).

Abstract: A current limiting circuit (70) controls the leakage current of a memory circuit (24) of a portable wireless device (10) while operating in a standby mode. A first semiconductor well (64) isolates the memory circuit (24) that is disposed in a second semiconductor well (66) from a substrate (62). In the standby mode the current limiting circuit (70) is switched to a non-conduction mode that limits the leakage currents of a diode formed by the first semiconductor well (66) with the second semiconductor well (64) and a diode formed by the second semiconductor well (64) with the substrate (62).

Abstract: An SRAM memory cell (40) uses GCMOS transistors (42, 44, 56, and 58) for improving discharge of complementary bit lines (60 and 62). The GCMOS transistors (42, 44, 56, and 58) have a graded-channel region on only the source side of the transistors. Configuring the pass-transistors (56 and 58) having the drain terminals connected to the complementary bit lines (60 and 62) and the cross-coupled transistors (42 and 44) having drain terminals connected to the memory cell outputs improves timing for a read operation of the memory cell (40).

Abstract: A circuit and method modify data stored in a storage element (30) of a memory circuit (110) when high voltages used for such modification exceed transistor breakdowns. A charge pump (302) produces a pumped voltage (V.sub.P1) for modifying the data. A monitor circuit (304) produces an enable signal (V.sub.PEN) to activate other power supply voltages when the pumped voltage reaches a predetermined voltage level for allowing the data to be modified. A routing circuit (832) selects between the pumped voltage and a first voltage (V.sub.DD) in response to a first control signal (HVENABLEP) to produce a selected voltage. A switching circuit (802-808) passes the selected voltage to the storage element (30) to modify the data when the first supply voltage is selected by the routing circuit.

Abstract: A memory circuit (24) includes a sense amp circuit (30) that uses multiplexers (86) in a column mux (32) for pre-charging only selected bitlines in order to limit the current during a read operation of the FLASH memory circuit (24). The sense amp circuit (30) provides the bitline with a pre-charge voltage that is set by a current reference (68) that is substantially supply independent. In the read mode the sense amp circuit (30) responds to either a voltage on the bitline that is lowered from the pre-charge voltage value by a selected programmed memory cell (40) or by a voltage that remains at the pre-charged voltage value for an unprogrammed memory cell.

Abstract: A circuit (10) for enhancing logic transitions appearing on a line (34) has been provided. The circuit includes a first comparator (14) for sensing when a voltage on the line exceeds a first level and subsequently pulling the voltage on the line to a first predetermined voltage. The circuit also includes a second comparator (12) for sensing when the voltage on the line falls below a second level and subsequently pulling the voltage on the line to a second predetermined voltage.

Abstract: A transmitter/receiver circuit (19) for interfacing digital signals having logic levels of different voltage ranges. The transmitter/receiver circuit comprises a transmitter circuit (21) , a resistive load (23) , and a receiver circuit (22). The transmitter circuit (21) having a first input (24) which receives a digital signal of a first voltage range, a second input (26) which receives a control signal, a first terminal (27) and a second terminal (28). The resistive load (23) couples the first (27) and second (28) outputs together. The transmitter circuit (21) generates complementary digital signals at the first terminal (27) and the second terminal (28) having logic levels of a second voltage range. The transmitter circuit (21) can be disabled by the control signal. The receiver circuit (22) has a first and a second input coupled to the first (27) and second (28) terminals respectively and has an output (29).

Abstract: A digital voltage level translator circuit for interfacing circuitry operating at different voltages is described. An inverting digital voltage level translator circuit (11) has an input (12) and an output (13). The input is coupled to a transmission gate (18), an inverter (17), and a gate of a n-channel enhancement MOSFET (22). Transmission gate (18) is enabled by the inverter (17) when the input (12) is at a zero logic level. An output of transmission gate (18) is coupled to a gate of a p-channel enhancement MOSFET (21) and an output of a pull-up circuit (19). A zero logic level at the input (12) enables MOSFET (21) through transmission gate (18) and disables MOSFET (22) generating a one logic level at output (12). A one logic level at the input (12) enables MOSFET (22) transitioning output (13) to a zero logic level. Output (13) to a control input of pull-up circuit (19) and a zero logic level enables pull-up circuit (19) disabling MOSFET (21).