Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

Abstract: An apparatus for gathering queue performance data includes an event conditioning logic unit that receives a queue enter signal, a queue exit signal, and a queue not empty signal from a queue. The apparatus also includes a counter that may be both incremented and decremented. The event conditioning logic unit may be programmed to increment the counter upon occurrences of a predetermined combination of the queue signals. The event conditioning logic unit may also be programmed to decrement the counter upon occurrences of an additional predetermined combination of the queue signals.

Abstract: A memory controller hub has a data stream controller adapted to use a system memory to store graphics data and to control functions of the system memory, a processor interface, a system memory interface, a graphics subsystem coupled to the data stream controller and adapted to perform graphics operations on graphics data, and a graphics port adapted to couple the memory controller hub to an external graphics device.

Abstract: An integrated circuit chip includes counters. Each one of the counters counts data events, There are a plurality of registers associated with the counters. At lease one of the registers controls the stopping, starting and counting of an associated counter. A command trigger issues a command to the register upon the detection of a hardware event. The command initiates the starting, stopping or counting of the counter associated with the register.

Abstract: An integrated circuit chip includes performance counters. Each one of the performance counters counts data events. There are a plurality of registers associated with the performance counters. At least one of the registers controls the stopping, starting and counting of an associated performance counter. A command trigger issues a command to the register upon the detection of a hardware event. The command initiates the starting, stopping or counting of the counter associated with the register.

Abstract: An apparatus for gathering queue performance data includes an event conditioning logic unit that receives a queue enter signal, a queue exit signal, and a queue not empty signal from a queue. The apparatus also includes a counter that may be both incremented and decremented. The event conditioning logic unit may be programmed to increment the counter upon occurrences of a predetermined combination of the queue signals. The event conditioning logic unit may also be programmed to decrement the counter upon occurrences of an additional predetermined combination of the queue signals.