Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

Abstract: Disclosed herein are diamondoid materials in quantum computing devices, as well as related methods, devices, and materials. For example, in some embodiments, a quantum computing device may include: qubit circuitry, an interconnect in conductive contact with the qubit circuitry, and a dielectric material proximate to the interconnect, wherein the dielectric material includes a diamondoid film.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

Abstract: Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

Abstract: Quantum dot devices with independent gate control are disclosed. An example quantum dot device includes N parallel rows of gate lines provided over a quantum well stack. Each of the N parallel rows of gate lines defines a respective row of a quantum dot formation region in the quantum well stack and includes M parallel gate lines stacked above one another. The quantum dot device may further include, for each of the N×M gate lines, a gate that extends toward the quantum well stack, where, for an individual row of the N parallel rows, gates that extend toward the quantum well stack from the M parallel stacked gate lines are arranged above a respective row of a quantum dot formation region in the quantum well stack. In this manner, each of the N×M gates responsible for formation of different quantum dots may be controlled independently.

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

Abstract: Quantum dot devices with three of more accumulation gates provided over a single row of a quantum dot formation region are disclosed. Each accumulation gate is electrically coupled to a respective doped region. In this manner, multiple single electron transistors (SETs) are provided along the row. Side and/or center screening gates may be used to apply microwave pulses for qubit control and to control electrostatics so that source and drain regions of the multiple SETs with quantum dots formed along the single row of a quantum dot formation region are sufficiently isolated from one another. Such quantum dot devices provide strong spatial localization of the quantum dots, good control over quantum dot interactions and manipulation, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ?1 and the core material exhibits a second resistivity ?2 and ?2 is less than ?1.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate and an adjacent second gate above the quantum well stack; and a gate wall between the first gate and the second gate, wherein the gate wall includes a spacer and a capping material, the spacer has a top and a bottom, the bottom of the spacer is between the top of the spacer and the quantum well stack, and the capping material is proximate to the top of the spacer.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.

Abstract: Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.