Abstract: A noninverting transistor switch having only a first terminal, a second terminal and a third terminal includes a transistor connected to the second and third terminals, the transistor having an on switching state in which current is able to pass between the second and third terminals and an off switching state in which current is interrupted from passing between the second and third terminals. The transistor switch also includes a voltage stabilizer connected to the second and third terminals. The transistor switch further includes a CMOS inverter connected to the first terminal, the second terminal, the transistor and the voltage stabilizer. In use, the CMOS inverter interrupts the passing of current between the voltage stabilizer and the second terminal when the transistor is in its off switching state.

Abstract: A noninverting transistor switch having only a first terminal, a second terminal and third terminal includes a transistor connected to the second and third terminals, the transistor having an on switching state in which current is able to pass between the second and third terminals and an off switching state in which current is interrupted from passing between the second and third terminals. The transistor switch also includes a voltage stabilizer connected to the second and third terminals. The transistor switch further includes a CMOS inverter connected to the first terminal, the second terminal, the transistor and the voltage stabilizer. In use, the CMOS inverter interrupts the passing of current between the voltage stabilizer and the second terminal when the transistor is in its off switching state.

Abstract: A timer switch for suspending the application of a direct current input voltage to a load upon the detection of a voltage irregularity in the input voltage. The timer switch includes a transistor switch for selectively connecting the input voltage to the load. The timer switch also includes a timing element which detects the presence of a voltage irregularity in the input voltage and controls the state of the transistor switch based upon the detection of a voltage irregularity in the input voltage. The timer switch includes exactly three terminals and is powered by the input voltage. The timing element includes exactly one energy storage element which is represented as a capacitor.

Abstract: An inverting hysteretic transistor switch having an input terminal, an output terminal and a ground terminal includes, in some embodiments, a metal-oxide semiconductor field effect transistor (MOSFET) having an on switching state and an off switching state. The MOSFET includes a drain terminal connected to the output terminal, a gate terminal and a source terminal connected to the ground terminal. The switch further includes a hysteresis circuit connected to the input terminal and to the gate terminal of the MOSFET. In use, with an input voltage having low-to-high and high-to-low input voltage transitions applied to the input terminal, the hysteresis circuit switches the MOSFET to its on switching state at a first threshold voltage during low-to-high input voltage transitions. In addition, the hyteresis circuit switches the MOSFET to its off switching state at a second threshold voltage, which is less than the first threshold voltage, during high-to-low input voltage transitions.

Abstract: A driver-sensor circuit for a circuit-testing device has a sensor amplifier (Q1, Q2, Q3, and Q4) for sensing the voltage on a device under test connected to its input-output terminal (12). The driver-sensor circuit also includes a driver amplifier (Q5, Q6, Q7, and Q8) for driving the same terminal (12). The driver amplifier (Q5, Q6, Q7, and Q8) can be switched on and off, and a limiting amplifier (Q9, Q10, Q11, and Q12) applies the sensor-amplifier output voltage to the input terminal (20) of the driver circuit (Q5, Q6, Q7, and Q8) to keep the reverse bias on the driver-amplifier transistors (Q5, Q6, Q7, and Q8) to a minimum. To eliminate offset bias current at the input terminal 12 of the sense amplifier (Q1, Q2, Q3, and Q4), compensation transistors (Q15, Q16 ) matching the input-stage transistors (Q1, Q2) of the driver amplifier have their bases tied together to force their base currents to cancel.

Abstract: A DC amplifier uses complementary npn and pnp output transistors on n-type and p-type substrates, respectively. The output transistors are in an emitter-follower configuration with no emitter resistor to prevent thermal runaway. Instead, emitter-follower driver-stage transistors are provided on the same substrates as the output transistors to force a reduction in the bias voltage on the output stage when the temperature of an output transistor increases. This circuit prevents thermal runaway and temperature-dependent offsets without emitter resistors, which would increase output impedance, and without feedback from the output stage to the input stage, which would slow the response of the amplifier. Additionally, compensation-network transistors are provided to eliminate offsets resulting from driver- and output-transistor base-to-emitter voltage differences caused not only by temperature differences between the transistors on different substrates but also by manufacturing variations.

Abstract: A high current lateral transistor suitable for intergrated circuit construction is fabricated in the form of a plurality of parallel transistors. Each transistor has an emitter surrounded by a closely confronting collector with the intervening semiconductor acting as the base region. Groups of parallel connected transistors are located on both sides of and distributed along a centerline which contains a number of diffused crossunder resistor elements. Each group of transistors is flanked on both sides by a base contact that is extended perpendicularly away from the centerline and connected by metalization to a resistor element. The resistor elements act to distribute the transistor base currents in a ballasting operation that promotes proper current distribution. Since the resistors are under the oxide the emitter and collector metalization can pass across the centerline region and parallel connect the individual transistors.

Abstract: Method and circuitry for generating signals in response to an input signal whose frequency or pulse rate is to be measured, which signals are directly applicable to the coils of an air core type meter movement or the like to provide an output indication of the frequency or pulse rate of the input signal. The signals applied to the air core meter are generated directly from the input signal and include sine and cosine signals synchronous with the input signal. A preferred embodiment is disclosed which includes circuitry which produces staircase waveforms, which when integrated, produce the required sine and cosine signals to drive an air core meter movement in response to a periodic input signal.

Abstract: In an amplifier circuit the output devices are thermally coupled to a shutdown circuit. A first latch is designed to operate at a first high temperature excursion. The first latch operation acts to shut the output devices off and to invoke a second latch. The second latch operates between a low temperature and a second high temperature that is below the first high temperature. Thus, after the first latch operates, the second latch will operate to cycle between a low temperature whereupon it energizes the output devices and a high temperature at which it deenergizes the output devices. By this action, the circuit will permit only one high temperature peak after which it will cycle between a lower high temperature peak and a low temperature. This avoids repeated cycling to a high temperature that could be deleterious to the circuit devices or the package in which they are housed.

Abstract: In an integrated circuit class B audio output device the transistors are fabricated as plural parallel connected sections. The two output transistors have their sections interdigitated so that adjacent sections are not turned on simultaneously. This leads to substantial improvements in thermal peaks within the transistors and to reduced thermal gradients across the transistors.

Abstract: A high power integrated circuit amplifier employs emitter ballasted NPN output transistors. One output transistor is driven by a PNP transistor to create a composite pair. Since the ballast resistor, in the composite pair, is effectively in the collector of a PNP equivalent transistor, the output stage creates substantial distortion. The output stage is driven by a conventional high gain capacitance compensated amplifier. By connecting an additional negative feedback capacitor between the emitter of the composite pair output transistor and the driver amplifier input, the distortion can be effectively compensated without resorting to power dissipative distortion reduction.