Abstract: Embodiments of a substrate are provided herein, which include: a first metal plane and a second metal plane in a first metal layer, the first and second metal planes laterally separated by a first gap of dielectric material; and a third metal plane and a fourth metal plane in a second metal layer vertically adjacent to the first metal layer, the third and fourth metal planes laterally separated by a second gap of dielectric material, wherein the second gap comprises a first laterally-shifted gap portion and a second laterally-shifted gap portion, the first laterally-shifted gap portion is laterally offset from a vertical footprint of the first gap in a first lateral direction, and the second laterally-shifted gap portion is laterally offset from the vertical footprint of the first gap in a second lateral direction opposite the first lateral direction.

Abstract: A semiconductor device includes a package substrate, a semiconductor die attached to a first major surface of the package substrate, and a plurality of wire bonds attached between the semiconductor die and the first major surface of the package substrate. The device further includes a conductive plate over the semiconductor die, plurality of wire bonds, and package substrate wherein a first major surface of the conductive plate faces the first major surface of the package substrate. The device further includes a plurality of conductive extensions attached to the first major surface of the conductive plate, wherein each conductive extension extends from the first major surface of the conductive plate and between two adjacent wire bonds of the plurality of wire bonds.

Abstract: Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a first major surface of the substrate; a second flip chip die mounted to the first major surface of the substrate, the second flip chip die laterally adjacent to the first flip chip die on the first major surface; and a wire bond formed between a first bond pad on the first flip chip die and a second bond pad on the second flip chip die.

Abstract: Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a first major surface of the substrate; a second flip chip die mounted to the first major surface of the substrate, the second flip chip die laterally adjacent to the first flip chip die on the first major surface; and a wire bond formed between a first bond pad on the first flip chip die and a second bond pad on the second flip chip die.

Abstract: A simulation monitor (502) automatically generates a monitor file (510) from a static timer output file (504). The monitor file instantiates a function, a firing equation, that triggers if and only if a critical timing path also triggers. The monitor file is written in a high level language description, suitable for efficient simulation. The test vectors which trigger the firing equation can thereby be monitored and used for hardware test at a later time. The invention may be extended to monitor other conditions of interest.

Abstract: In a multi-processing system (10), a cache controller is implemented to efficiently process collisions which occur when a predetermined address location in a data memory (26) is simultaneously accessed by two processors (20, 21). The cache controller is formed by both a cache control logic circuit (34) and a tag unit (36). In the tag unit (36), a snoop tag cache (40) and a data tag cache (42) respectively indicate whether a snooped value or an accessed data value is stored in data memory (26). A status bit array (41) provides status information for both tag caches (40, 42). By configuring the array (41) to store status information for both snoop and data tag caches (40, 42), status information is "forwarded" between tag caches (40, 42) when a collision occurs. Additionally, the cache controller modifies the timing of each of the accesses such that the status information may be "forwarded" more easily. The timing modification is also referred to as "resource pipelining.

Abstract: A sense amplifier with an integral logic function for use in a circuit such as a tag cache portion of a microprocessor cache. In one form, the integral logic function is an exclusive-OR function. The sense amplifier senses a differential voltage developed between a differential pair of bit lines which are coupled to predetermined bit positions of a plurality of entries in a tag cache. While sensing the voltage, an exclusive-OR function is performed between the logic state of the sensed bit and a corresponding input address bit. If the input address bit matches the sensed bit, then a match signal is asserted. The value of the corresponding input address bit configures the circuit either to provide an output signal in a predetermined logic state if a true bit line signal voltage exceeds a complement bit line signal voltage, or to provide the output signal in the predetermined state if the complement bit line signal voltage exceeds the true bit line signal voltage.

Abstract: A sense amplifier for fast and reliable sensing of a small voltage differential is accomplished by the integration of a latch which uses regenerative feedback. Complementary devices are used within the sense amplifier to modify its configuration from an amplifier to a latch. The integration of the latch for gain allows the use of a single-ended sense amplifier section, as opposed to requiring a double-ended design for level shifting and symmetrical sensing of `0` and `1`. The output is a pair of full-rail complementary signals that can be directly used by standard CMOS logic downstream.

Abstract: An integrated circuit has a signature circuit which provides information concerning the integrated circuit itself. This information can, for example, specify that redundancy has or has not been implemented. Other potential information can relate to the particular mask set, the speed of the integrated circuit, and/or the manufacturer. The information is provided on a normal output terminal of the integrated circuit. A load is selectively coupled to the output terminal in response to an input signal of the integrated circuit if a particular node is programmed to a first logic state. If the particular node is programmed to a second logic state, the load is not responsive to the input signal. A load variation then indicates one condition of the integrated circuit, and no load variation indicates another condition. Numerous outputs can be similarly used to provide additional amounts of information according to some selected code.

Abstract: A redundant decoder for use in a predecoded memory scheme includes a plurality of predecoding circuits each having an output and each having inputs coupled to selected address signals. The outputs of the predecoding circuits are applied to the inputs of a smaller group of decoding circuit. In addition, the outputs of the predecoding circuits are coupled to the gate electrodes of one of a plurality of series coupled field effect transistors each having a laser blowable fuse coupled across its source drain path. Should one of the decoding circuits prove to be operating improperly, is only necessary to blow the fuses across the individual field effect transistors whose gate electrodes are coupled to the predecoding circuit outputs which served as inputs to the bad gate. In this manner, the output of the stack will go high only when the output of the bad decoding circuit should go high.

Abstract: A circuit for generating a pulse in response to an address transition using an input NOR gate to initiate the generation of the pulse. A delay circuit provides a delayed signal for actively terminating the pulse after a predetermined time period. An inhibit circuit is used to prevent the delayed signal from attempting to actively terminate the pulse when there has been another address transition, thereby saving power.