Patents by Inventor James S. Griffth

James S. Griffth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5524263
    Abstract: A method and apparatus for handling resource allocation during processor stall conditions. The instruction issue components of a processor are stalled (e.g., the issuance of new instruction is frozen) as a result of various stall conditions. One stall condition (full stall) occurs when an allocated buffer resource becomes full. Another stall condition (partial stall) occurs during register renaming and a given instruction sources a larger register width than the register alias table currently contains within the RAT buffer. This is a partial width data dependency and a partial stall is asserted. The present invention, upon detection of a full stall, does not allocate any buffer entries within the clock cycle that causing the full stall and resource pointers are not advanced and instructions issued during that clock cycle are not allocated. Within the clock cycle of the deassertion of the full stall, the resource buffers are allocated and the resource allocation pointers are updated.
    Type: Grant
    Filed: February 25, 1994
    Date of Patent: June 4, 1996
    Assignee: Intel Corporation
    Inventors: James S. Griffth, Shantanu R. Gupta, Narayan Hegde