Abstract: A test and measurement instrument including a splitter configured to split an input signal having a particular bandwidth into a plurality of split signals, each split signal including substantially the entire bandwidth of the input signal; a plurality of harmonic mixers, each harmonic mixer configured to mix an associated split signal of the plurality of split signals with an associated harmonic signal to generate an associated mixed signal; and a plurality of digitizers, each digitizer configured to digitize a mixed signal of an associated harmonic mixer of the plurality of harmonic mixers. A first-order harmonic of at least one harmonic signal associated with the harmonic mixers is different from an effective sample rate of at least one of the digitizers.

Abstract: A test and measurement instrument including a splitter configured to split an input signal having a particular bandwidth into a plurality of split signals, each split signal including substantially the entire bandwidth of the input signal; a plurality of harmonic mixers, each harmonic mixer configured to mix an associated split signal of the plurality of split signals with an associated harmonic signal to generate an associated mixed signal; and a plurality of digitizers, each digitizer configured to digitize a mixed signal of an associated harmonic mixer of the plurality of harmonic mixers. A first-order harmonic of at least one harmonic signal associated with the harmonic mixers is different from an effective sample rate of at least one of the digitizers.

Abstract: A balun structure is disclosed having positive and negative going signal paths coupled to a ninety degree hybrid. The positive signal path has a circuit trace and a phase shaper structure that provides three hundred and sixty degrees of phase shift at Port 1 of the hybrid. The negative going signal path has a circuit trace and a second order phase shaper that provides four hundred and fifty degrees of phase shift at Port 2 of the hybrid. Port 1 is coupled to Port 3 of the hybrid and functions as an output port. The first order phase shaper and the second order phase shaper compensate for the signal loss caused by a signal cable coupled to the output port and provide a frequency band from DC to at least 15 GHz and a transient response having less than ten percent pre-shoot.

Abstract: A balun structure is disclosed having positive and negative going signal paths coupled to a ninety degree hybrid. The positive signal path has a circuit trace and a phase shaper structure that provides three hundred and sixty degrees of phase shift at Port 1 of the hybrid. The negative going signal path has a circuit trace and a second order phase shaper that provides four hundred and fifty degrees of phase shift at Port 2 of the hybrid. Port 1 is coupled to Port 3 of the hybrid and functions as an output port. The first order phase shaper and the second order phase shaper compensate for the signal loss caused by a signal cable coupled to the output port and provide a frequency band from DC to at least 15 GHz and a transient response having less than ten percent pre-shoot.

Abstract: An all NPN transistor level-shifting differential amplifier has first and second identical amplifier halves, in which each amplifier half includes a passive voltage-shifting network coupled between a load and a current source. A main amplifier has a single-ended voltage input and an output coupled to the first node of the voltage shifting network. An output amplifier has a single-ended current output and an input coupled to the second node of the voltage shifting network. The main amplifier and output amplifiers are coupled together such that a portion of the bias and signal currents flowing through the output amplifier is reused and flows through the main amplifier, reducing bias current and power requirements. The first and second amplifier halves are coupled together with a gain-setting emitter resistor. In addition to reducing the power requirements of the amplifier, the feedback configuration of the level-shifting amplifier also increases linearity over prior art level-shifting amplifiers.

Abstract: An f.sub.T doubler amplifier having a Darlington type common base stage is provided wherein the fast current contributions from the f.sub.T doubler are passed through the slow path of the Darlington common base stage, and the slow current contributions from the f.sub.T doubler are passed through the fast path of the Darlington common base in order that the delay of each current contribution is more closely matched. In this way, the distributed nature of the amplifier and resultant phase distortion are minimized and transient response is improved.

Abstract: A clock-delay circuit for a sinusoidal clock output includes a pair of current amplifiers, each connected to the clock output, wherein one of the amplifiers generates an amplified signal in phase with the clock output and the other generates a signal shifted in phase by 90.degree.. Both signals are multiplied by control signals to alter their respective amplitudes prior to summation of both multiplier outputs. The sum of the multiplier outputs will be a sinusoidal waveform whose phase depends upon the control currents in the multipliers which are set by the user. Thus, the circuit provides a user-controlled continuously variable delay for a sinusoidal clock.

Abstract: A variable transient response control for linear integrated-circuit high-frequency amplifiers comprises a variable equivalent resistive damping network interposed in the signal transmission path, and an electronic control circuit therefor. The resistive network includes preferably Schottky diodes having low inductance and a determinable equivalent resistance in the forward conducting condition.

Abstract: A serial DAC comprises two shift registers having their data input terminals connected together for receiving serial binary data. The shift registers are clocked alternately, whereby each shift register is clocked at substantially half the rate at which data is applied to the data input terminals of the shift registers. Two current switches are associated with the shift registers respectively, each switch being operative to steer input current to one of two output terminals if the data output of the associated shift register is a digital 1 and to steer input current to the other output terminal if the data output is a digital 0. Two current sources supply equal, constant currents to input terminals of the two current switches respectively.

Abstract: A restart circuit for a digital processor is disclosed. A regularly serviced processor signal is continuously monitored and if an intermittant soft failure of the processor occurs, causing the processor signal to go high or low or toggle in an irregular fashion, a restart pulse is automatically generated. Thus, with the occurrence of a soft failure, the operator no longer has to manually reset the processor system.