Patents by Inventor James S. Sims
James S. Sims has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210384028Abstract: A method for depositing a silicon nitride layer on a stack is provided. The method comprises providing an atomic layer deposition, comprising a plurality of cycles, wherein each cycle comprises dosing the stack with a silicon containing precursor by providing a silicon containing precursor gas, providing an N2 plasma conversion, and providing an H2 plasma conversion.Type: ApplicationFiled: October 11, 2019Publication date: December 9, 2021Inventors: James S. SIMS, Shane TANG, Vikrant RAI, Andrew MCKERROW, Huatan QIU
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Patent number: 10020188Abstract: A method of depositing ALD films on semiconductor substrates processed in a micro-volume of a plasma enhanced atomic layer deposition (PEALD) reaction chamber wherein a single semiconductor substrate is supported on a ceramic surface of a pedestal and process gas is introduced through gas outlets in a ceramic surface of a showerhead into a reaction zone above the semiconductor substrate, includes (a) cleaning the ceramic surfaces of the pedestal and showerhead with a fluorine plasma such that aluminum-rich byproducts are formed on the ceramic surfaces, (b) depositing a conformal halide-free atomic layer deposition (ALD) oxide undercoating on the ceramic surfaces so as to cover the aluminum-rich byproducts, (c) depositing a pre-coating on the halide-free ALD oxide undercoating, and (d) processing a batch of semiconductor substrates by transferring each semiconductor substrate into the reaction chamber and depositing a film on the semiconductor substrate supported on the ceramic surface of the pedestal.Type: GrantFiled: November 20, 2017Date of Patent: July 10, 2018Assignee: LAM RESEARCH CORPORATIONInventors: James S. Sims, Jon Henri, Ramesh Chandrasekharan, Andrew John McKerrow, Seshasayee Varadarajan, Kathryn Merced Kelchner
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Publication number: 20180102245Abstract: A method of depositing ALD films on semiconductor substrates processed in a micro-volume of a plasma enhanced atomic layer deposition (PEALD) reaction chamber wherein a single semiconductor substrate is supported on a ceramic surface of a pedestal and process gas is introduced through gas outlets in a ceramic surface of a showerhead into a reaction zone above the semiconductor substrate, includes (a) cleaning the ceramic surfaces of the pedestal and showerhead with a fluorine plasma such that aluminum-rich byproducts are formed on the ceramic surfaces, (b) depositing a conformal halide-free atomic layer deposition (ALD) oxide undercoating on the ceramic surfaces so as to cover the aluminum-rich byproducts, (c) depositing a pre-coating on the halide-free ALD oxide undercoating, and (d) processing a batch of semiconductor substrates by transferring each semiconductor substrate into the reaction chamber and depositing a film on the semiconductor substrate supported on the ceramic surface of the pedestal.Type: ApplicationFiled: November 20, 2017Publication date: April 12, 2018Applicant: LAM RESEARCH CORPORATIONInventors: James S. Sims, Jon Henri, Ramesh Chandrasekharan, Andrew John McKerrow, Seshasayee Varadarajan, Kathryn Merced Kelchner
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Patent number: 9824884Abstract: A method of depositing silicon nitride films on semiconductor substrates processed in a micro-volume of a plasma enhanced atomic layer deposition (PEALD) reaction chamber wherein a single semiconductor substrate is supported on a ceramic surface of a pedestal and process gas is introduced through gas outlets in a ceramic surface of a showerhead into a reaction zone above the semiconductor substrate, includes (a) cleaning the ceramic surfaces of the pedestal and showerhead with a fluorine plasma, (b) depositing a halide-free atomic layer deposition (ALD) oxide undercoating on the ceramic surfaces, (c) depositing a precoating of ALD silicon nitride on the halide-free ALD oxide undercoating, and (d) processing a batch of semiconductor substrates by transferring each semiconductor substrate into the reaction chamber and depositing a film of ALD silicon nitride on the semiconductor substrate supported on the ceramic surface of the pedestal.Type: GrantFiled: October 6, 2016Date of Patent: November 21, 2017Assignee: LAM RESEARCH CORPORATIONInventors: James S. Sims, Jon Henri, Ramesh Chandrasekharan, Andrew John McKerrow, Seshasayee Varadarajan, Kathryn Merced Kelchner
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Patent number: 9659769Abstract: A highly tensile dielectric layer is generated on a heat sensitive substrate while not exceeding thermal budget constraints. Ultraviolet (UV) irradiation is used to produce highly tensile films to be used, for example, in strained NMOS transistor architectures. UV curing of as-deposited PECVD silicon nitride films, for example, has been shown to produce films with stresses of at least 1.65 E10 dynes/cm2. Other dielectric capping layer film materials show similar results. In transistor implementations, the stress from a source/drain region capping layer composed of such a film is uniaxially transferred to the NMOS channel through the source-drain regions to create tensile strain in the NMOS channel.Type: GrantFiled: October 22, 2004Date of Patent: May 23, 2017Assignee: Novellus Systems, Inc.Inventors: Bhadri Varadarajan, Sean Chang, James S. Sims, Guangquan Lu, David Mordo, Kevin Ilcisin, Mandar Pandit, Michael Carris
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Patent number: 9598770Abstract: Semiconductor processing chamber showerheads with contoured faceplates, as well as techniques for producing such faceplates, are provided. Data describing deposition rate as a function of gap distance between a reference showerhead faceplate and a reference substrate may be obtained, as well as data describing deposition rate as a function of location on the substrate when the reference showerhead and the reference substrate are in a fixed arrangement with respect to each other. The two data sets may be used to determine offsets from a reference plane associated with the faceplate that determine a contour profile to be used with the faceplate.Type: GrantFiled: March 18, 2016Date of Patent: March 21, 2017Assignee: Novellus Systems, Inc.Inventors: Karl F. Leeser, James S. Sims
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Patent number: 9589790Abstract: Provided herein are methods of depositing conformal silicon nitride films using atomic layer deposition by exposure to a halogen-free, N—H-bond-free, and carbon-free silicon-containing precursor such as disilane, purging of the precursor, exposure to a nitrogen plasma, and purging of the plasma at low temperatures. A high frequency plasma is used, such as a plasma having a frequency of at least 13.56 MHz or at least 27 MHz. Methods yield substantially pure conformal silicon nitride films suitable for deposition in semiconductor devices, such as in trenches or features, or for memory encapsulation.Type: GrantFiled: November 24, 2014Date of Patent: March 7, 2017Assignee: Lam Research CorporationInventors: Jon Henri, Dennis M. Hausmann, Shane Tang, James S. Sims
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Publication number: 20160203953Abstract: Semiconductor processing chamber showerheads with contoured faceplates, as well as techniques for producing such faceplates, are provided. Data describing deposition rate as a function of gap distance between a reference showerhead faceplate and a reference substrate may be obtained, as well as data describing deposition rate as a function of location on the substrate when the reference showerhead and the reference substrate are in a fixed arrangement with respect to each other. The two data sets may be used to determine offsets from a reference plane associated with the faceplate that determine a contour profile to be used with the faceplate.Type: ApplicationFiled: March 18, 2016Publication date: July 14, 2016Inventors: Karl F. Leeser, James S. Sims
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Publication number: 20160148806Abstract: Provided herein are methods of depositing conformal silicon nitride films using atomic layer deposition by exposure to a halogen-free, N—H-bond-free, and carbon-free silicon-containing precursor such as disilane, purging of the precursor, exposure to a nitrogen plasma, and purging of the plasma at low temperatures. A high frequency plasma is used, such as a plasma having a frequency of at least 13.56 MHz or at least 27 MHz. Methods yield substantially pure conformal silicon nitride films suitable for deposition in semiconductor devices, such as in trenches or features, or for memory encapsulation.Type: ApplicationFiled: November 24, 2014Publication date: May 26, 2016Inventors: Jon Henri, Dennis M. Hausmann, Shane Tang, James S. Sims
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Patent number: 9315899Abstract: Semiconductor processing chamber showerheads with contoured faceplates, as well as techniques for producing such faceplates, are provided. Data describing deposition rate as a function of gap distance between a reference showerhead faceplate and a reference substrate may be obtained, as well as data describing deposition rate as a function of location on the substrate when the reference showerhead and the reference substrate are in a fixed arrangement with respect to each other. The two data sets may be used to determine offsets from a reference plane associated with the faceplate that determine a contour profile to be used with the faceplate.Type: GrantFiled: July 3, 2012Date of Patent: April 19, 2016Assignee: Novellus Systems, Inc.Inventors: Karl F. Leeser, James S. Sims
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Patent number: 9214333Abstract: Disclosed herein are methods of depositing a SiN film having a reduced wet etch rate. The methods may include adsorbing a film precursor comprising Si onto a semiconductor substrate in a processing chamber to form an adsorption-limited layer of precursor, and then removing unadsorbed precursor from the volume surrounding the adsorbed precursor. The adsorbed precursor may then be reacted by exposing it to a plasma comprising N-containing ions and/or radicals to form a SiN film layer on the substrate, and the SiN film layer may then be densified by exposing it to a He plasma. The foregoing steps may then be repeated to form another densified SiN film layer on the substrate. Also disclosed herein are apparatuses for depositing SiN films having reduced wet etch rates on semiconductor substrates which employ the foregoing techniques.Type: GrantFiled: September 24, 2014Date of Patent: December 15, 2015Assignee: Lam Research CorporationInventors: James S. Sims, Kathryn M. Kelchner, Jon Henri, Dennis M. Hausmann
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Patent number: 9076646Abstract: The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes using pulsed plasmas. While conventional PEALD processes use continuous wave plasmas during the plasma exposure/conversion operation, the embodiments herein utilize a pulsed plasma during this operation to achieve a film with high quality sidewalls. Because conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls, this increased sidewall quality in the disclosed methods corresponds to a film that is overall more uniform in quality compared to that achieved with conventional continuous wave plasma techniques.Type: GrantFiled: December 30, 2013Date of Patent: July 7, 2015Assignee: Lam Research CorporationInventors: James S. Sims, Jon Henri, Kathryn M. Kelchner, Sathish Babu S. V. Janjam, Shane Tang
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Publication number: 20140113457Abstract: The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes using pulsed plasmas. While conventional PEALD processes use continuous wave plasmas during the plasma exposure/conversion operation, the embodiments herein utilize a pulsed plasma during this operation to achieve a film with high quality sidewalls. Because conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls, this increased sidewall quality in the disclosed methods corresponds to a film that is overall more uniform in quality compared to that achieved with conventional continuous wave plasma techniques.Type: ApplicationFiled: December 30, 2013Publication date: April 24, 2014Inventors: James S. Sims, Jon Henri, Kathryn M. Kelchner, Sathish Babu S. V. Janjam, Shane Tang
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Publication number: 20130334344Abstract: Semiconductor processing chamber showerheads with contoured faceplates, as well as techniques for producing such faceplates, are provided. Data describing deposition rate as a function of gap distance between a reference showerhead faceplate and a reference substrate may be obtained, as well as data describing deposition rate as a function of location on the substrate when the reference showerhead and the reference substrate are in a fixed arrangement with respect to each other. The two data sets may be used to determine offsets from a reference plane associated with the faceplate that determine a contour profile to be used with the faceplate.Type: ApplicationFiled: July 3, 2012Publication date: December 19, 2013Inventors: Karl F. Leeser, James S. Sims
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Patent number: 8512818Abstract: A highly tensile dielectric layer is generated on a heat sensitive substrate while not exceeding thermal budget constraints. Cascaded ultraviolet (UV) irradiation is used to produce highly tensile films to be used, for example, in strained NMOS transistor architectures. Successive UV radiation of equal or shorter wavelengths with variable intensity and duration selectively breaks bonds in the Si—N matrix and minimizes shrinkage and film relaxation. Higher tensile stress than a non-cascaded approach may be obtained.Type: GrantFiled: June 1, 2012Date of Patent: August 20, 2013Assignee: Novellus Systems, Inc.Inventors: Bhadri Varadarajan, Gengwei Jiang, Sirish K. Reddy, James S. Sims
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Patent number: 8362571Abstract: Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.Type: GrantFiled: January 28, 2011Date of Patent: January 29, 2013Assignee: Novellus Systems, Inc.Inventors: Qingguo Wu, James S. Sims, Mandyam Sriram, Seshasayee Varadarajan, Haiying Fu, Pramod Subramonium, Jon Henri, Sirish Reddy
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Patent number: 8211510Abstract: A highly tensile dielectric layer is generated on a heat sensitive substrate while not exceeding thermal budget constraints. Cascaded ultraviolet (UV) irradiation is used to produce highly tensile films to be used, for example, in strained NMOS transistor architectures. Successive UV radiation of equal or shorter wavelengths with variable intensity and duration selectively breaks bonds in the Si—N matrix and minimizes shrinkage and film relaxation. Higher tensile stress than a non-cascaded approach may be obtained.Type: GrantFiled: August 31, 2007Date of Patent: July 3, 2012Assignee: Novellus Systems, Inc.Inventors: Bhadri Varadarajan, Gengwei Jiang, Sirish K. Reddy, James S. Sims
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Patent number: 7998881Abstract: Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide boron doped carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.Type: GrantFiled: June 6, 2008Date of Patent: August 16, 2011Assignee: Novellus Systems, Inc.Inventors: Qingguo Wu, James S. Sims, Mandyam Sriram, Seshasayee Varadarajan, Akhil Singhal
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Patent number: 7906817Abstract: Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.Type: GrantFiled: June 6, 2008Date of Patent: March 15, 2011Assignee: Novellus Systems, Inc.Inventors: Qingguo Wu, James S. Sims, Mandyam Sriram, Seshasayee Varadarajan, Haiying Fu, Pramod Subramonium, Jon Henri, Sirish Reddy
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Patent number: 7745346Abstract: A method for forming a silicon-based dielectric film on a substrate with a single deposition process operation using pulsed plasma enhanced chemical vapor deposition (PECVD) wherein the high frequency radio frequency power of the plasma is pulsed, allows enhanced control, efficiency and product quality of the PECVD process. Pulsing the high frequency RF power of the plasma reduces the deposited film thickness per unit time the high frequency RF power of the plasma is on. This yields silicon-based dielectric films that are both thin and conformal.Type: GrantFiled: October 17, 2008Date of Patent: June 29, 2010Assignee: Novellus Systems, Inc.Inventors: Dennis Hausmann, James S. Sims, Andrew Antonelli, Sesha Varadarajan, Bart Van Schravendijk