Patents by Inventor James Satsuo Yamaguchi

James Satsuo Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7127807
    Abstract: A method is disclosed for providing electrical connections to electronic elements within a multilayer module. The method includes providing first and second active layers having first and second edges, respectively. Each active layer includes a flexible, polymer substrate and at least one electronic element formed within the substrate. Electrically-conductive traces provide electrical connections from the first and second edges to the electronic elements. An adhesive is applied to at least one of a top surface of the first active layer and a bottom surface of the second active layer and the top surface of the first active layer is adhered to the bottom surface of the second active layer. The first edge and the second edge are aligned with each other thereby forming a side of the multilayer module. Electrically-conductive lines are applied along the side of the multilayer module to provide electrical connections to the traces.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: October 31, 2006
    Assignee: Irvine Sensors Corporation
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
  • Patent number: 6797537
    Abstract: A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: September 28, 2004
    Assignee: Irvine Sensors Corporation
    Inventors: Angel Antonio Pepe, James Satsuo Yamaguchi
  • Patent number: 6784547
    Abstract: A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 31, 2004
    Assignee: Irvine Sensors Corporation
    Inventors: Angel Antonio Pepe, James Satsuo Yamaguchi
  • Patent number: 6734370
    Abstract: A multilayer module includes a first active layer with a first edge and second active layer with a second edge. Each active layer includes a flexible, polymer substrate, at least one electronic element, and a plurality of electrically-conductive traces which provide electrical connection from the respective edge to the electronic element of the active layer. The second active layer is adhered to the first active layer so that the first edge and second edge are aligned with each other thereby forming a side of the multilayer module. The multilayer module further includes a plurality of electrically-conductive lines along the side of the multilayer module, the lines providing electrical connection to the traces.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: May 11, 2004
    Assignee: Irvine Sensors Corporation
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
  • Patent number: 6717061
    Abstract: Each multilayer module of a plurality of multilayer modules has a plurality of layers wherein each layer has a substrate therein. The plurality of multilayer modules includes a first multilayer module including a first layer and a second multilayer module including a second layer each having a top side and bottom side. The first layer and second layer each includes a substrate, at least one electronic element, and a plurality of electrically-conductive traces. The plurality of multilayer modules further includes a heat-separating layer disposed between the top side of the first layer and the bottom side of the second layer. The first multilayer module is adhered to the second multilayer module and the first multilayer module can be detached from the second multilayer module by applying heat to the heat-separating layer.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: April 6, 2004
    Assignee: Irvine Sensors Corporation
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
  • Publication number: 20040040743
    Abstract: A multilayer module includes a first active layer with a first edge and second active layer with a second edge. Each active layer includes a flexible, polymer substrate, at least one electronic element, and a plurality of electrically-conductive traces which provide electrical connection from the respective edge to the electronic element of the active layer. The second active layer is adhered to the first active layer so that the first edge and second edge are aligned with each other thereby forming a side of the multilayer module. The multilayer module further includes a plurality of electrically-conductive lines along the side of the multilayer module, the lines providing electrical connection to the traces.
    Type: Application
    Filed: May 7, 2003
    Publication date: March 4, 2004
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
  • Publication number: 20030127735
    Abstract: A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.
    Type: Application
    Filed: November 21, 2002
    Publication date: July 10, 2003
    Inventors: Angel Antonio Pepe, James Satsuo Yamaguchi
  • Patent number: 6560109
    Abstract: A stack of multilayer modules has a segmentation layer disposed between neighboring multilayer modules. The segmentation layer facilitates the separation of neighboring multilayer modules. The stack of multilayer modules includes a first multilayer module and a second multilayer module. Each multilayer module includes a plurality of active layers each comprising a substrate, at least one electronic element, and a plurality of electrically-conductive traces. The second multilayer module is disposed to be neighboring the first multilayer module with at least one segmentation layer between the first and second multilayer modules. The segmentation layer includes a metal layer and at least one thermoplastic adhesive layer. When heat is applied, the metal layer conducts heat to the thermoplastic adhesive layer.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: May 6, 2003
    Assignee: Irvine Sensors Corporation
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
  • Publication number: 20030080419
    Abstract: A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.
    Type: Application
    Filed: October 30, 2001
    Publication date: May 1, 2003
    Inventors: Angel Antonio Pepe, James Satsuo Yamaguchi
  • Publication number: 20030049424
    Abstract: Each multilayer module of a plurality of multilayer modules has a plurality of layers wherein each layer has a substrate therein. The plurality of multilayer modules includes a first multilayer module including a first layer and a second multilayer module including a second layer each having a top side and bottom side. The first layer and second layer each includes a substrate, at least one electronic element, and a plurality of electrically-conductive traces. The plurality of multilayer modules further includes a heat-separating layer disposed between the top side of the first layer and the bottom side of the second layer. The first multilayer module is adhered to the second multilayer module and the first multilayer module can be detached from the second multilayer module by applying heat to the heat-separating layer.
    Type: Application
    Filed: September 7, 2001
    Publication date: March 13, 2003
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
  • Publication number: 20030049889
    Abstract: A method fabricates multilayer modules with flexible substrates. The method includes stacking a plurality of active layer sheets and a plurality of segmentation layer sheets with adhesive between the layer sheets, thereby assembling an arrayed module pre-form. Each segmentation layer sheet includes a thermally-conductive material. The method further includes stacking a plurality of arrayed module pre-forms with at least one segmentation layer sheet between each pair of arrayed module pre-forms and with a thermoplastic adhesive material applied to the segmentation layer sheets. The method further includes laminating the active layer sheets and the segmentation layer sheets together, cutting the stack of arrayed multilayer modules, forming electrically-conductive lines along at least one side of the stack of multilayer modules, and segmenting the stack of multilayer modules into individual multilayer modules.
    Type: Application
    Filed: September 7, 2001
    Publication date: March 13, 2003
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
  • Publication number: 20030047353
    Abstract: A multilayer module includes a first active layer with a first edge and second active layer with a second edge. Each active layer includes a flexible, polymer substrate, at least one electronic element, and a plurality of electrically-conductive traces which provide electrical connection from the respective edge to the electronic element of the active layer. The second active layer is adhered to the first active layer so that the first edge and second edge are aligned with each other thereby forming a side of the multilayer module. The multilayer module further includes a plurality of electrically-conductive lines along the side of the multilayer module, the lines providing electrical connection to the traces.
    Type: Application
    Filed: September 7, 2001
    Publication date: March 13, 2003
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien
  • Publication number: 20030048609
    Abstract: A stack of multilayer modules has a segmentation layer disposed between neighboring multilayer modules. The segmentation layer facilitates the separation of neighboring multilayer modules. The stack of multilayer modules includes a first multilayer module and a second multilayer module. Each multilayer module includes a plurality of active layers each comprising a substrate, at least one electronic element, and a plurality of electrically-conductive traces. The second multilayer module is disposed to be neighboring the first multilayer module with at least one segmentation layer between the first and second multilayer modules. The segmentation layer includes a metal layer and at least one thermoplastic adhesive layer. When heat is applied, the metal layer conducts heat to the thermoplastic adhesive layer.
    Type: Application
    Filed: September 7, 2001
    Publication date: March 13, 2003
    Inventors: James Satsuo Yamaguchi, Angel Antonio Pepe, Volkan H. Ozguz, Andrew Nelson Camien