Patents by Inventor James Schleicher
James Schleicher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11487927Abstract: A system having design tools and methods for using the same in designing an integrated circuit (IC) are described.Type: GrantFiled: October 12, 2020Date of Patent: November 1, 2022Assignee: EFINIX, INC.Inventor: James Schleicher
-
Publication number: 20210042462Abstract: A system having design tools and methods for using the same in designing an integrated circuit (IC) are described.Type: ApplicationFiled: October 12, 2020Publication date: February 11, 2021Inventor: James Schleicher
-
Patent number: 10803225Abstract: A system having design tools and methods using the same design tools in designing an integrated circuit (IC) are described.Type: GrantFiled: January 24, 2019Date of Patent: October 13, 2020Assignee: EFINIX, INC.Inventor: James Schleicher
-
Publication number: 20200242210Abstract: A system having design tools and methods for using the same in designing an integrated circuit (IC) are described.Type: ApplicationFiled: January 24, 2019Publication date: July 30, 2020Inventor: James Schleicher
-
Patent number: 10177766Abstract: Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.Type: GrantFiled: November 14, 2016Date of Patent: January 8, 2019Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy L. Lee, Rahul Saini, Henry Kim
-
Patent number: 9496875Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.Type: GrantFiled: September 30, 2014Date of Patent: November 15, 2016Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy L. Lee, Rahul Saini, Henry Kim
-
Patent number: 8878567Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.Type: GrantFiled: October 24, 2013Date of Patent: November 4, 2014Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy L. Lee, Rahul Saini, Henry Kim
-
Patent number: 8593174Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.Type: GrantFiled: June 29, 2012Date of Patent: November 26, 2013Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy Lee, Rahul Saini, Henry Kim
-
Patent number: 8237465Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.Type: GrantFiled: March 17, 2011Date of Patent: August 7, 2012Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy Lee, Rahul Saini, Henry Kim
-
Patent number: 7911230Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.Type: GrantFiled: April 16, 2009Date of Patent: March 22, 2011Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy Lee, Rahul Saini, Henry Kim
-
Patent number: 7839167Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: GrantFiled: January 20, 2009Date of Patent: November 23, 2010Assignee: Altera CorporationInventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
-
Patent number: 7671625Abstract: Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.Type: GrantFiled: March 5, 2008Date of Patent: March 2, 2010Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Michael Hutton, Andy Lee, Rahul Saini, Henry Kim
-
Publication number: 20090289660Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: ApplicationFiled: January 20, 2009Publication date: November 26, 2009Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
-
Patent number: 7594208Abstract: Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.Type: GrantFiled: December 13, 2006Date of Patent: September 22, 2009Assignee: Altera CorporationInventors: Terry Borer, Ian Chesal, James Schleicher, David Mendel, Mike Hutton, Boris Ratchev, Yaska Sankar, Babette van Antwerpen, Gregg Baeckler, Richard Yuan, Stephen Brown, Vaughn Betz, Kevin Chan
-
Patent number: 7565388Abstract: Logic circuits that support the addition of three binary numbers using hardwired adders are described. In one embodiment, this is accomplished by using a 3:2 compressor (i.e., a Carry Save Adder method), using hardwired adders to add the sums and carrys produced by the 3:2 compression, and sharing carrys data calculated in one logic element (“LE”) with the following LE. In such an embodiment, with the exception of the first and last LEs in a logic array block (“LAB”), each LE in effect lends one look-up table (“LUT”) to the LE below (i.e., the following LE) and borrows one LUT from the LE above (i.e., the previous LE). The LUT being lent or borrowed is one that implements the carry function in the 3:2 compressor model. In another aspect, an embodiment of the present invention provides LEs that include selectors to select signals corresponding to the addition of three binary numbers mode.Type: GrantFiled: November 21, 2003Date of Patent: July 21, 2009Assignee: Altera CorporationInventors: Gregg Baeckler, Martin Langhammer, James Schleicher, Richard Yuan
-
Patent number: 7538579Abstract: Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.Type: GrantFiled: December 1, 2006Date of Patent: May 26, 2009Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy Lee, Rahul Saini, Henry Kim
-
Patent number: 7492188Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: GrantFiled: July 30, 2007Date of Patent: February 17, 2009Assignee: Altera CorporationInventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
-
Publication number: 20080074143Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: ApplicationFiled: July 30, 2007Publication date: March 27, 2008Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter Kazarian, Andrew Leaver, David Mendel, Jim Park
-
Patent number: 7317332Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: GrantFiled: November 7, 2005Date of Patent: January 8, 2008Assignee: Altera CorporationInventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Victor Maruri, Rakesh Patel
-
Publication number: 20070294659Abstract: Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.Type: ApplicationFiled: August 16, 2007Publication date: December 20, 2007Inventors: James Schleicher, David Karchmer