Abstract: A data processing system is provided with a first mechanism for executing instructions of a first instruction set and a second mechanism for executing instructions of a second instruction set. The second mechanism requires configuration data 310, 312, 314, 316 which may or may not be valid. Programs that use the second execution mechanism are responsible for the writing of its own configuration data with this being indicated as being necessary by a configuration valid indicator CV set to indicate that the configuration is invalid by the operating system 300 upon detecting an appropriate process switch.

Abstract: A data processing apparatus 2 is provided which supports two instruction sets. These two instruction sets share a common subset of instructions including at least one class of instructions, such as all of the coprocessor instructions. The common subset of instructions have the same instruction encoding once any differences due to storage order within memory have been compensated for e.g. endianness.

Abstract: A data processing system 2 is provided supporting address offset generating instructions which encode bits of an address offset value using previously redundant bits in a legacy instruction encoding whilst maintaining backwards compatibility with that legacy encoding.

Abstract: A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilising a 12-bit offset field but with a fixed addressing mode and a second form utilising a shorter 8-bit offset field but with an addressing mode specified within a manipulation mode control field of the data access instruction.

Abstract: Within a data processing system 2 prediction instructions 30 are provided which add conditional behaviour to associated program instructions 26, 28.

Abstract: A data processing apparatus 2 supports multiple memory access program instructions LDM, STM which serve to load data values from multiple program registers 16 to respective memory locations or to store data values from multiple memory locations to respective program registers. A memory management unit 8 within the system stores device or strongly ordered memory attribute values which control whether or not a multiple memory access instruction involving such a memory location may be early terminated when an interrupt is received during its operation. Early termination is permitted in those circumstances where the multiple memory access instruction may be safely restarted and rerun in its entirety, whereas early termination is not permitted and the operation completes before the interrupt is taken in those circumstances where the memory locations are subject to a guaranteed number of memory accesses as this appears within the controlling program instructions.

Abstract: The position of a radio frequency identification (RFID) transponder may be determined with respect to a plurality of stationary sensors located in an array within certain physical areas. Each sensor comprises a plurality of antenna coils arranged in unique physical orientations and capable of transmitting radio frequency signals of differing phase. The RFID transponder includes an antenna which receives the plurality of signals generated by the antenna coils, and compares the phase of at least two of the signals to determine the relative position of the transponder. The location of the transponder with respect to two or more sensor(s) may also be determined through measurement of the intensity of the signals received by the antenna coil of the transponder. The system and method may also transmit data between a sensor and a dormant (motionless) RFID transponder using a hand-held high intensity RF probe.

Abstract: A system and method for determining the position of a radio frequency identification (RFID) transponder with respect to a sensor. In one embodiment, the system comprises a plurality of stationary sensors located in an array within certain physical areas. Each sensor comprises a plurality of antenna coils arranged in unique physical orientations and capable of transmitting radio frequency signals of differing phase. The RFID transponder includes an antenna which receives the plurality of signals generated by the antenna coils, and compares the phase of at least two of the signals to determine the relative position of the transponder. In a second aspect of the invention, the aforementioned antenna coils emit two direction finding mode (DFM) signals in succession; the first signal with all antenna coils turned on, the second with one of the coils turned off.

Abstract: The present invention provides a system, method and computer program for performing a modular multiplication a*b*2−N modulo n, where a, b and n are N-bit integers. The system comprises a multiplier for multiplying a Y-bit number by a Z-bit number, and partitioning logic for partitioning the integer a into a plurality of first sections, each first section being of a size which is a multiple of Y, and for partitioning the integer b into a plurality of second sections, each second section being of a size which is a multiple of Z. A multiplication unit is then provided to apply operations to control the multiplier to perform a sequence of multiplications to multiply one of said first sections by one of said second sections in order to generate a number of output operands for use in subsequent operations performed by the multiplication unit.

Abstract: A data processing apparatus and method is provided for applying a floating-point multiply-accumulate operation to first, second and third operands. The apparatus comprises a multiplier for multiplying the second and third operands and applying rounding to produce a rounded multiplication result, and an adder for adding the rounded multiplication result to the first operand to generate a final result and for applying rounding to generate a rounded final result. Further, control logic is provided which is responsive to a first single instruction to control the multiplier and adder to cause the rounded final result generated by the adder to be equivalent to the subtraction of the rounded multiplication result from the first operand.

Abstract: A data processing system is provided with a first mechanism for executing instructions of a first instruction set and a second mechanism for executing instructions of a second instruction set. The second mechanism requires configuration data 310, 312, 314, 316 which may or may not be valid. Programs that use the second execution mechanism are responsible for the writing of its own configuration data with this being indicated as being necessary by a configuration valid indicator CV set to indicate that the configuration is invalid by the operating system 300 upon detecting an appropriate process switch.

Abstract: A data processing system supports execution of both native instructions and Java bytecodes using a hardware executer for the Java bytecodes where possible and a software instruction interpreter for the Java bytecodes where these are not supported by the hardware. The sequences of native instructions 26 within the software instruction interpreter that perform the processing for the Java bytecodes being interpreted terminate within a sequence terminating instruction BXJ that acts differently depending upon whether or not an enabled hardware executer 6 is detected to be present. If an enabled hardware executer is detected as present, then the execution of the next Java bytecode is attempted with this. If an active hardware executer is not present, then the next Java bytecode is passed directly to the software instruction interpreter.

Abstract: The system comprises a plurality of stationary sensors located in an array within certain physical areas. Each sensor comprises a plurality of antenna coils arranged in unique physical orientations and capable of transmitting radio frequency signals of differing phase. The RFID transponder includes an antenna which receives the signals generated by the antenna coils, and compares the phase of at least two of the signals to determined the relative position of the transponder. The antenna coils may emit two direction finding mode (DFM) signals in succession; the first signal with all antenna coils turned on, the second with a subset of the coils turned off. The spatial relationship of the transponder antenna and individual antenna coils precludes all of the signals in each sensor from being rejected by the transponder during emission of both the first and second DFM signal.

Abstract: The present invention relates to a data processing apparatus and method for saturating data values. The data processing apparatus comprises a data processing unit for executing instructions, the data processing unit being responsive to a saturation instruction to apply a saturation operation to a data word Rm comprising a plurality of data values. The saturation operation yields a value given by: determining from data provided within a field of the saturation instruction a bit position to which saturation is to take place, and performing in parallel an independent saturation operation on each of the data values to saturate each of the data values to the determined bit position to form a result data word Rd comprising a plurality of saturated data values. This techniques provides a particularly efficient and flexible technique for saturating multiple data values.

Abstract: A system and method for determining the position of a radio frequency identification (RFID) transponder with respect to a sensor. In one embodiment, the system comprises a plurality of stationary sensors located in an array within certain physical areas. Each sensor comprises a plurality of antenna coils arranged in unique physical orientations and capable of transmitting radio frequency signals of differing phase. The RFID transponder includes an antenna which receives the plurality of signals generated by the antenna coils, and compares the phase of at least two of the signals to determine the relative position of the transponder. In a second aspect of the invention, the aforementioned antenna coils emit two direction finding mode (DFM) signals in succession; the first signal with all antenna coils turned on, the second with one of the coils turned off.

Abstract: A data processing system is provided with an instruction (ADD8TO16) that unpacks non-adjacent portions of a data word using sign or zero extension and combines this with a single-instruction-multiple-data type arithmetic operation, such as an add, performed in response to the same instruction. The instruction is well suited to use within systems having a data path (2) including a shifting circuit (6) upstream of an arithmetic circuit (8).

Abstract: A data processing system is provided for supporting saturating arithmetic using input operands of the Q31 and Q15 type. In order to accommodate this type of operation applied to multiply accumulate or multiply subtract instructions, additional instructions QDADD, QDSUB and QDRSB are provided, QDADD provides the function of double/saturate/add/saturate. QDSUB and QDRSB provide respective operand orderings of double/saturate/subtract/saturate operations. Providing these special purpose instructions within the instruction set allows the required saturation and adjustments to be provided for Q31 and Q15 operands whilst not imposing additional delays and complication onto the main data paths required for the rest of the processing operations.

Abstract: A floating point unit is provided with a register bank comprising 32 registers that may be used as either vector registers of scalar registers. A data processing instruction includes at least one register specifying field pointing to a register containing a data value to be used in that operation. An increase in the instruction bit space available to encode more opcodes or to allow for more registers is provided by encoding whether a register is to be treated as a vector or a scalar within the register field itself. Further, the register field for one register of the instruction may encode whether another register is a vector or a scalar. The registers can be initially accessed using the values within the register fields of the instruction independently of the opcode allowing for easier decode.

Abstract: A floating point unit having a register bank containing a plurality of registers supports vector operations that execute a specified operation a plurality of times upon a sequence of data values form different registers. The register bank is divided into subsets and with the sequence of registers used in a vector operation wrapping within a subset. The subsets comprise disjoint, contiguous ranges of register numbers. The wrapping within ranges allows compact code and efficient to be provided for performing DSP operations, such as FIR filtering and matrix transformations.

Abstract: A floating point unit is described that performs addition operations. An adder 16 within the floating point unit receives a first input and a second input to generate a sum. This sum is subject to subsequent normalization by a normalizer 60 and rounding by an incrementer 64. If an operation is performed that is immediately followed by an addition operation using the result of the preceding operation, then the normalized but unrounded sum is fed back to the adder 16 together with an indication of its rounding requirement. This rounding requirement can be performed by the adder 16 in parallel with the execution of the following addition by using the carry-in bit of the adder 16 to apply any increment required to rounding of the preceding result.