Abstract: This invention discloses a method for identifying, tracking persons and objects of interest (POI) across multiple monitored areas through means of electromagnetic radiation, sounds and any other sensory inputs in conjunction of location data of electronic devices in the monitored areas. The methodology includes collecting anthropometric data, metrological measurements and any other data relating to persons and objects of interest and location data of electronic devices in the monitored areas. Applying multiple pattern recognition algorithms and statistical analysis of location data to the persons and objects of interests, the system can deduce and focus on the persons and objects of interest's location, movements across monitor areas of the system.

Abstract: Techniques are disclosed for determining a preferred hashing algorithm for load balancing physical interface utilization in a network device, such as a switch, configured with a port-channel architecture. While a current hashing algorithm is being applied to network traffic flows, a forwarding engine of the network device retrieves snapshot data of each flow and evaluates the flows against other hashing algorithms. The forwarding engine, for each hashing algorithm result, calculates statistical measures, such as mean, variance, and coefficient of variation. These measures are used to determine the preferred hashing algorithm to subsequently be applied. Once determined, the networking device may notify a user (e.g., a system administrator) of the algorithm.

Abstract: Techniques are disclosed for determining a preferred hashing algorithm for load balancing physical interface utilization in a network device, such as a switch, configured with a port-channel architecture. While a current hashing algorithm is being applied to network traffic flows, a forwarding engine of the network device retrieves snapshot data of each flow and evaluates the flows against other hashing algorithms. The forwarding engine, for each hashing algorithm result, calculates statistical measures, such as mean, variance, and coefficient of variation. These measures are used to determine the preferred hashing algorithm to subsequently be applied. Once determined, the networking device may notify a user (e.g., a system administrator) of the algorithm.

Abstract: Techniques for controlling visibility settings of data entities (for example but not limited to item listings, items, products and services, stock keeping units (SKUs) reviews, collections, lists, adverts, etc.) on a networked commerce system are described. According to various embodiments, a seller specification of an item is received, via a user interface, in connection with a request to post item information on a networked commerce system. Entity visibility compliance rules regarding the online sale of items in one or more regions are then accessed. Thereafter, the item specified by the seller is determined to be subject to a particular entity visibility compliance rule in a particular region. An entity visibility setting may then be adjusted for that item information throughout the networked commerce system in that particular region, based on the particular entity visibility compliance rule.

Abstract: A method for estimating the geographical latitude, longitude and elevation of a mobile electronic telecommunication device (TD) is provided. The method draws random information over a given time period from multiple responders. A triangulation and signal quality analysis is performed to determine the possible location of the TD. Using the statistical information and its analysis the location (x, y and z coordinates) as well as the velocity and acceleration of the device is estimated. The present invention provides extremely accurate location information.

Abstract: A method for estimating the geographical latitude, longitude and elevation of a mobile electronic telecommunication device (TD) is provided. The method draws random information over a given time period from multiple responders. A triangulation and signal quality analysis is performed to determine the possible location of the TD. Using the statistical information and its analysis the location (x, y and z coordinates) as well as the velocity and acceleration of the device is estimated. The present invention provides extremely accurate location information.

Abstract: A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.

Abstract: A fitting for joining a corrugated conduit to a structure associated therewith is disclosed. The fitting comprises a hollow body having an inner chamber and at least two body resilient tabs extending from an end. The at least two body resilient tabs define at least two body gaps therebetween. Each of the at least two body resilient tabs defines an outwardly extending detent. The fitting also comprises a retaining ring including a flange and at least two ring resilient tabs extending from the flange and defining ring gaps therebetween. Each of the at least two ring resilient tabs defines an inwardly extending detent adapted to engage a corrugated conduit. Each of the at least two body resilient tabs is selectively inserted in a corresponding one of the at least two ring gaps, and the outwardly extending detents selectively engage an end of the flange of the retaining ring.

Abstract: The present invention relates to a speech cancellation system for actively reducing the audibility to nearby persons of the voice of the user into a personal communication device.

Abstract: A fitting for joining a corrugated conduit to a structure associated therewith is disclosed. The fitting comprises a hollow body having an inner chamber and at least two body resilient tabs extending from an end. The at least two body resilient tabs define at least two body gaps therebetween. Each of the at least two body resilient tabs defines an outwardly extending detent. The fitting also comprises a retaining ring including a flange and at least two ring resilient tabs extending from the flange and defining ring gaps therebetween. Each of the at least two ring resilient tabs defines an inwardly extending detent adapted to engage a corrugated conduit. Each of the at least two body resilient tabs is selectively inserted in a corresponding one of the at least two ring gaps, and the outwardly extending detents selectively engage an end of the flange of the retaining ring.

Abstract: A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.

Abstract: A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.

Abstract: A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.

Abstract: A method of fabricating a non-volatile memory embedded logic circuit having a low voltage logic gate oxide layer and tunnel oxide layer is described. Both the low voltage logic gate oxide and the tunnel oxide layers are formed in a single step, thereby reducing the number of overall processing steps needed to form the devices.

Abstract: The present invention is a non-volatile memory embedded logic circuit and method of fabrication having a low voltage logic gate oxide layer that has essentially the same thickness as the tunnel oxide layer of the non-volatile memory cell. Consequently, both said oxide layers can be formed in a single step, thereby reducing the number of processing steps needs to form the overall device.

Abstract: A composition is provided which is useful for the polishing of a semiconductor wafer substrate comprising an organic polymer having a backbone comprised of at least 16 carbon atoms, the polymer having a plurality of moieties with affinity to surface groups on the semiconductor wafer surface. Another composition is provided which is useful for the polishing of a semiconductor wafer substrate comprising a surfactant having a carbon chain backbone comprised of at least 16 carbon atoms.

Abstract: An aqueous polishing composition for chemical mechanical polishing of semiconductor devices of silica and circuits of aluminum, titanium or titanium nitride; wherein said aqueous composition includes, an oxidizing agent, an inhibitor of a polyalkyleneimine, and a pH buffer, and a method for polishing a semiconductor device by applying the polishing composition at an interface between a polishing pad and the semiconductor device.