Abstract: An apparatus includes a base and a coating disposed on the base. A therapeutic agent is disposed on at least one of the base or the coating. A vibration device is coupled to the base. The vibration device is configured to cause movement of the base such that at least a portion of the therapeutic agent is released from the base or the coating. A method includes inserting a stent into a body lumen of a patient. The stent has a base, a coating disposed on at least a portion of the base, and a therapeutic agent carried by at least one of the base or the coating. The stent is vibrated such that at least a portion of the therapeutic agent is released from the stent.

Abstract: According to an aspect of the present invention, medical devices are provided, which are adapted for implantation or insertion into a subject and which include at least one multilayer region that contains multiple charged layers of alternating charge. The multiple charged layers, in turn, include the following: (i) at least one charged block copolymer (e.g., a charged block copolymer that contains one or more polyelectrolyte blocks) and (ii) at least one charged therapeutic agent (e.g., a charged therapeutic agent that contains one or more polyelectrolyte blocks).

Abstract: An apparatus and method for field-injection electrostatic spray deposition of medical devices like stents. The apparatus includes a medical device holder, which applies a first electrical potential to the medical device, and an electrically insulative electrostatic spray dispensing device having an electrically conductive electrode, which applies a second electrical potential, creating an electrical potential difference sufficient to attract charged coating material particles emitted from an orifice of the dispensing device toward the medical device. The electrode may be sharpened to create a localized, high-strength electric field to improve the charge injection into the coating material or coating solution.

Abstract: A system for protecting a stent includes an electroactive polymer (EAP) sleeve, a stent, a balloon catheter, and a voltage source. A voltage is applied to the EAP sleeve, whereupon the EAP sleeve expands. The stent, disposed about the balloon catheter is inserted into the region defined by the inner surface of the EAP sleeve. The voltage is removed, whereupon the EAP sleeve contracts.

Abstract: The stent placement dilation balloon assembly comprises a catheter having a distal end, a distal end portion, and a proximal end, a balloon mounted to, about, and around the distal end portion of the catheter. The assembly further includes an elastic sheath positioned about and around the balloon. The outer surface of the sheath includes a profile which encourages stent securement. A stent is mounted on the sleeve for placement in a vessel in a human body.

Abstract: Medical devices, for example, those that have balloons, and methods of making the devices are described. For example, in some embodiments, a medical device includes an elongated shaft, and an inflatable balloon carried by the shaft. The balloon includes a first recessed channel, a second recessed channel, a third recessed channel, and a fourth recessed channel, wherein the first recessed channel is spaced from the second recessed channel by a first distance, the third recessed channel is spaced from the fourth recessed channel by the first distance, and the second recessed channel is spaced from the third recessed channel by a second distance different than the first distance.

Abstract: Medical devices, for example, those that have balloons, and methods of making the devices are described. In some embodiments, a method includes providing a medical balloon having a first cone portion and a body portion, and removing material from an outer surface the body portion of the balloon such that the balloon includes a first region and a second region, the first region being recessed relative to the second region.

Abstract: A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline.

Abstract: A method, processor, and data processing system implementing a delayed reject mechanism are disclosed. The processor includes an issue unit suitable for issuing an instruction in a first cycle and a load store unit (LSU). The LSU includes an extend reject calculator circuit configured to receive a set of completion information signals and generate a delay value based thereon. The LSU is adapted to determine whether to reject the instruction in a determination cycle. The number of cycles between the first cycle and the determination cycle is a function of the delay value such that reject timing is variable with respect to the first cycle. In one embodiment, the processor is further configured to reissue the instruction after the determination cycle if the instruction was rejected in the determination cycle. The delay value is conveyed via a 2-bit bus in one embodiment. The 2 bit bus permits delaying the determination cycle from 0 to 3 cycles after a finish cycle.

Abstract: A processor and an associated method and data processing system are disclosed. The processor includes an issue unit (ISU), a completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is adapted to produce a completion valid signal responsive to the issue unit completing an instruction. The hang detect unit is configured to receive the completion valid signal from the ISU and adapted to determine the interval since the most recent assertion of the completion valid signal. The hang detect unit is adapted to initiate a hang recovery sequence upon determining that the interval since the most recent assertion of the completion valid signal exceeds a predetermined maximum interval. In one embodiment, the hang recovery sequence includes the hang recovery unit asserting a stop completion signal to a completion unit and a stop dispatch signal to a dispatch unit to suspend instruction completion and dispatch.

Abstract: A method for optimally issuing instructions that are related to a first instruction in a data processing system is disclosed. The processing system includes a primary and secondary cache. The method and system comprises speculatively indicating a hit of the first instruction in a secondary cache and releasing the dependent instructions. The method and system includes determining if the first instruction is within the secondary cache. The method and system further includes providing data related to the first instruction from the secondary cache to the primary cache when the instruction is within the secondary cache. A method and system in accordance with the present invention causes instructions that create dependencies (such as a load instruction) to signal an issue queue (which is responsible for issuing instructions with resolved conflicts) in advance, that the instruction will complete in a predetermined number of cycles.

Abstract: In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the program order of the load and store instructions. When a load instruction is issued for execution, a determination is made whether the load instruction is attempting to load data to a memory location that is the same as a previously executed store instruction is waiting to complete. If so, then the data waiting to be stored within the cache by the store instruction is directly forwarded to the load instruction.

Abstract: Pipelining and parallel execution of multiple load instructions is performed within a load store unit. When a first load instruction incurs a cache miss and proceeds to retrieve the load data from the system memory hierarchy, a second load instruction addressing the same load data will be merged into the first load instruction so that the data returned from the system memory hierarchy is sent to register files associated with both the first and second load instructions. As a result, the second load instruction does not have to wait until the load data has been written and validated in the data cache.

Abstract: In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit.

Abstract: A method and system for atomic memory accesses in a processor system, wherein the processor system is able to issue and execute multiple instructions out of order with respect to a particular program order. A first reservation instruction is speculatively issued to an execution unit of the processor system. Upon issuance, instructions queued for the execution unit which occur after the first reservation instruction in the program order are flushed from the execution unit, in response to detecting any previously executed reservation instructions in the execution unit which occur after the first reservation instruction in the program order.

Abstract: A superscalar processor and method are disclosed for efficiently recovering from misaligned data addresses. The processor includes a memory device partitioned into a plurality of addressable memory units. Each of the plurality of addressable memory units has a width of a first plurality of bytes. A determination is made regarding whether a data address included within a memory access instruction is misaligned. The data address is misaligned if it includes a first data segment located in a first addressable memory unit and a second data segment located in a second addressable memory unit where the first and second data segments are separated by an addressable memory unit boundary. In response to a determination that the data address is misaligned, a first internal instruction is executed which accesses the first memory unit and obtains the first data segment. A second internal instruction is executed which accesses the second memory unit and obtains the second data segment.

Abstract: A processor (100) includes an issue unit (125) having an issue queue (144) for issuing instructions to an execution unit (140). The execution unit (140) may accept and execute the instruction or produce a reject signal. After each instruction is issued, the issue queue (144) retains the issued instruction for a critical period. After the critical period, the issue queue (144) may drop the issued instruction unless the execution unit (140) has generated a reject signal. If the execution unit (140) has generated a reject signal, the instruction is eventually marked in the issue queue (144) as being available to be reissued. The length of time that the rejected instruction is held from reissue may be modified depending upon the nature of the rejection by the execution unit (140). Also, the execution unit (140) may conduct corrective actions in response to certain reject conditions so that the instruction may be fully executed upon reissue.

Abstract: A memory system wherein data retrieval is simultaneously initiated in both and L2 cache and main memory, which allows memory latency associated with arbitration, memory DRAM address translation, and the like to be minimized in the event that the data sought by the processor is not in the L2 cache (miss). The invention allows for any memory access to be interrupted in the storage control unit prior to any memory signals being activated. The L2 and memory access controls are in a single component, i.e. the storage control unit (SCU). Both the L2 and the memory have a unique port into the CPU which allows data to be directly transferred. This eliminates the overhead associated with storing the data in an intermediate device, such as a cache or memory controller.