Patents by Inventor James Simkins
James Simkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210401701Abstract: An antidandruff composition includes about 0.1 to about 1% by weight of a natural oil containing a mixture of C12 and C14 alkyl groups derived from coconut oil; about 6% by weight of a non-ionic surfactant having at least 16 carbon atoms; about 2% by weight of an antidandruff agent; about 1.5% by weight of a cationic surfactant; about 1.5% by weight of a quaternary ammonium salt; and at least 75% by weight of water. A method of making an antidandruff composition includes combining a natural oil containing a mixture of C12 and C14 alkyl groups, a non-ionic surfactant having at least 16 carbon atoms, an antidandruff agent, a cationic surfactant, a quaternary ammonium salt, and water, forming the antidandruff composition.Type: ApplicationFiled: June 24, 2020Publication date: December 30, 2021Applicant: Conopco, Inc., d/b/a UNILEVERInventors: Joshua Ryan Carew, Adam James Simkins, Amy Elizabeth Vanvelsor
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Publication number: 20060288069Abstract: An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.Type: ApplicationFiled: May 12, 2006Publication date: December 21, 2006Applicant: Xilinx, Inc.Inventors: James Simkins, Jennifer Wong, Bernard New, Alvin Ching, John Thendean, Anna Wong, Vasisht Vadi
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Publication number: 20060288070Abstract: A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.Type: ApplicationFiled: May 12, 2006Publication date: December 21, 2006Applicant: Xilinx, Inc.Inventors: Vasisht Vadi, Jennifer Wong, Bernard New, Alvin Ching, John Thendean, Anna Wong, James Simkins
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Publication number: 20060230092Abstract: A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.Type: ApplicationFiled: May 12, 2006Publication date: October 12, 2006Applicant: Xilinx, Inc.Inventors: Alvin Ching, Jennifer Wong, Bernard New, James Simkins, John Thendean, Anna Wong, Vasisht Vadi
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Publication number: 20060230094Abstract: An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.Type: ApplicationFiled: May 12, 2006Publication date: October 12, 2006Applicant: Xilinx, Inc.Inventors: James Simkins, Jennifer Wong, Bernard New, Alvin Ching, John Thendean, Anna Wong, Vasisht Vadi
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Publication number: 20060230093Abstract: An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.Type: ApplicationFiled: May 12, 2006Publication date: October 12, 2006Applicant: Xilinx, Inc.Inventors: Bernard New, Jennifer Wong, James Simkins, Alvin Ching, John Thendean, Anna Wong, Vasisht Vadi
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Publication number: 20060230096Abstract: An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.Type: ApplicationFiled: May 12, 2006Publication date: October 12, 2006Applicant: Xilinx, Inc.Inventors: John Thendean, Jennifer Wong, Bernard New, Alvin Ching, James Simkins, Anna Wong, Vasisht Vadi
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Publication number: 20060230095Abstract: A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.Type: ApplicationFiled: May 12, 2006Publication date: October 12, 2006Applicant: Xilinx, Inc.Inventors: James Simkins, John Thendean, Vasisht Vadi, Bernard New, Jennifer Wong, Anna Wong, Alvin Ching
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Publication number: 20060212499Abstract: A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.Type: ApplicationFiled: May 12, 2006Publication date: September 21, 2006Applicant: Xilinx, Inc.Inventors: Bernard New, Vasisht Vadi, Jennifer Wong, Alvin Ching, John Thendean, Anna Wong, James Simkins
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Publication number: 20060206557Abstract: An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.Type: ApplicationFiled: May 12, 2006Publication date: September 14, 2006Applicant: Xilinx, Inc.Inventors: Anna Wing Wah Wong, Jennifer Wong, Bernard New, Alvin Ching, John Thendean, James Simkins, Vasisht Mantra Vadi, David Schultz
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Publication number: 20060195496Abstract: An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.Type: ApplicationFiled: May 12, 2006Publication date: August 31, 2006Applicant: Xilinx, Inc.Inventors: Vasisht Vadi, Jennifer Wong, Bernard New, Alvin Ching, John Thendean, Anna Wong, James Simkins
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Publication number: 20060190516Abstract: A digital signal processing circuit including: a multiplier circuit; a plurality of. multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode.Type: ApplicationFiled: April 21, 2006Publication date: August 24, 2006Applicant: Xilinx, Inc.Inventors: James Simkins, Jennifer Wong, Bernard New, Alvin Ching, John Thendean, Anna Wong, Vasisht Vadi, David Schultz
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Publication number: 20050144213Abstract: Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M?1) and 2(M?1)?1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.Type: ApplicationFiled: December 21, 2004Publication date: June 30, 2005Applicant: Xilinx, Inc.Inventors: James Simkins, Steven Young, Jennifer Wong, Bernard New, Alvin Ching
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Publication number: 20050144212Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.Type: ApplicationFiled: December 21, 2004Publication date: June 30, 2005Applicant: Xilinx, Inc.Inventors: James Simkins, Steven Young, Jennifer Wong, Bernard New, Alvin Ching
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Publication number: 20050144216Abstract: Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.Type: ApplicationFiled: December 21, 2004Publication date: June 30, 2005Applicant: Xilinx, Inc.Inventors: James Simkins, Steven Young, Jennifer Wong, Bernard New, Alvin Ching
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Publication number: 20050144211Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.Type: ApplicationFiled: December 21, 2004Publication date: June 30, 2005Applicant: Xilinx, Inc.Inventors: James Simkins, Steven Young, Jennifer Wong, Bernard New, Alvin Ching
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Publication number: 20050144210Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.Type: ApplicationFiled: December 21, 2004Publication date: June 30, 2005Applicant: Xilinx, Inc.Inventors: James Simkins, Steven Young, Jennifer Wong, Bernard New, Alvin Ching
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Publication number: 20050144215Abstract: In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.Type: ApplicationFiled: December 21, 2004Publication date: June 30, 2005Applicant: Xilinx, Inc.Inventors: James Simkins, Steven Young, Jennifer Wong, Bernard New, Alvin Ching
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Patent number: 3933926Abstract: A process for the preparation of nitrophenols by adding over a period of time a suspension containing from about 4 to about 20 per cent weight/volume of nitrosated phenol to a nitric acid solution containing between 45 and 100 per cent by weight of nitric acid, said solution being maintained at a temperature in the range from about 45.degree. to 100.degree.C.Type: GrantFiled: May 30, 1973Date of Patent: January 20, 1976Inventors: David Anthony Salter, Robert John James Simkins