Abstract: A system and method increases signal strength at a receiver in transmission lines with high attenuation. The system comprises a transmitter for transmitting a pair of complementary oscillating voltage and timing references and a signal across transmission lines to a receiver. Since the references oscillate every bit time, the references do not suffer from the lone pulse problem but do suffer from attenuation. Since the signal may remain in a single state for several bit times, the signal may suffer from the lone pulse problem. The receiver maintains the references and the signal oscillating about a reference voltage, and compares the signal against the references. Based on the comparison, the receiver determines whether the current signal state has changed since the last signal state. Since the receiver compares one signal that suffers from the lone pulse problem against a reference that does not, signal strength is improved.

Abstract: A nonclock-synchronous interface between a microprocessor and a coprocessor. A request line (404) from the coprocessor and an acknowledgment line (402) from the microprocessor provide for operand transfer from the coprocessor to the microprocessor. A busy line (410) and an error line (408) from the coprocessor allow the microprocessor to monitor the condition of the coprocessor. Data (406) are transferred through a data channel in the microprocessor using the full memory management and protection mechanism of the microprocessor so that the protection mechanism is not circumvented. A memory-read cycle is generated using the address taken from the memory-address register (401). The data is buffered inside the microprocessor and the coprocessor's request is acknowledged. The memory-address register is then incremented by a predetermined amount and an I/O write cycle is generated using a prewired address into the coprocessor.