Abstract: Described are embodiments related to counter threat vector. A system includes two Linear Feedback Shift Registers (LFSR) of an equal size in the number of bits, initialized at power up or reset to an initial condition, wherein the values of the two LFSRs are compared during each clock cycle and if there is a mismatch an error is reported and threat mitigation initiated. This Abstract and the independent Claims are concise signifiers of embodiments of the claimed inventions. The Abstract does not limit the scope of the claimed inventions.

Abstract: Systems and circuits are disclosed for synchronizing processor clocks in a network of processors by using the method of Flit Rate Synchronization, where counts of flits (a unit of data) sent and received by processors are used to determine if a child processor in a network needs to increase or decrease the speed of its clock. Other systems and circuits are disclosed for Beacon Rate Synchronization that use a periodic beacon to eliminate relative drift between processors by applying a small adjustment to selected clock periods on a child processor in order to maintain a constant distance between arrival times of a periodic time beacon sent by a parent processor. This Abstract and the independent Claims are concise signifiers of embodiments of the claimed inventions. The Abstract does not limit the scope of the claimed inventions.

Abstract: In an IC chip, a novel precomputation architecture and process which grants improved reductions in power dissipation, requires less logic to implement, and relaxes critical timing constraints. A first computation circuit is used to calculate output values if precomputation cannot be performed. However, if the output values can be precomputed, a second circuit is used to calculate the output values. The second computation circuit is smaller, simpler, and consumes less power than the first computation circuit. An extremely small and simple decision circuit, which dissipates a minimal amount of power, is used to determine whether precomputation is possible. This determination is made at a previous cycle, whereas the actual computation of the output cycles are postponed to be performed in a subsequent cycle.

Abstract: A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell “library” within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e.g., input pin) caused the designated pin to transition.

Abstract: A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value.

Abstract: A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell "library" within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e.g., input pin) caused the designated pin to transition.

Abstract: A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value.

Abstract: A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular pin (e.g., input, output, bidirectional, internal) based on a prescribed condition of the state of signals that exist contemporaneously with a signal transition on the particular pin. This is referred to as state dependent power modeling. A different power consumption value can be provided for each different modeled state. The logic cells and the power consumption model for them are stored in a logic cell "library" within the computer system. State dependent power modeling of the present invention allows library designers to specify a different set of power values depending on the condition of one or more pins of the library cell (e.g., the library's representation of the logic cell).