Abstract: A multiprocessor data processing system includes an interconnect, a plurality of processing units coupled to the interconnect, and at least one system memory and a plurality of caches coupled to the plurality of processing units. A cache suitable for use in such a data processing system includes data storage containing multiple granules of data and a number of state fields associated with the granules of data. Each state field has a plurality of possible states including an O state indicating that an associated granule is consistent with corresponding data in the memory and has unknown coherency with respect to peer caches in the data processing system. Thus, a cache is permitted to store memory-consistent, but possibly non-coherent data in order to offer processing units in the data processing system lower latency to an image of system memory.

Abstract: A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster).

Abstract: A method and system for maintaining allocation information on data castout from an upper level cache provides a cache control with the ability to select victims based on whether a cache entry is present due to a read request from a higher level in the memory hierarchy or is present due to being modified in the higher level and then castout to the lower level. The information maintained may be a single bit indicating this status, may be a separate least-recently-used (LRU) array value indicating the order of allocation in the lower level for storage of cache entries castout from the higher level.

Abstract: A method and system for allocating lower level cache entries for data castout from an upper level cache provides improved computer system performance by adjusting the ordering of least-recently-used (LRU) information within a cache. Data that is castout from a higher level cache can be written after a read is satisfied and the castout entry will not be labeled as most-recently-used. This improves performance under certain operating conditions of a computing system, as castout data is often less important to keep in lower level cache than data that is also present in the higher level cache.

Abstract: A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster).

Abstract: A multiprocessor data processing system includes an interconnect, a plurality of processing units coupled to the interconnect, and at least one system memory and a plurality of caches coupled to the plurality of processing units. A cache suitable for use in such a data processing system includes data storage containing a data granule, a state field associated with the data granule, and a cache controller. The state field has a plurality of possible states including a first state that indicates that the data granule is consistent with corresponding data in the memory and has unknown coherency with respect to other peer caches among the plurality of caches. To update the state of the data granule from the first state, the cache controller issues on the interconnect a transaction specifying an address associated with the data granule. In response to receipt of a combined response of the plurality of caches, the cache controller updates the state field to a second state among the plurality of possible states.

Abstract: A method and system for bypassing cache levels when storing data castout from an upper level cache provides a memory hierarchy that can selectively skip one more more intermediate levels when writing castout entries from a higher level cache based on a number of detected conditions. The intermediate levels may be bypassed when an intermediate cache level is busy, has an entry with an address conflict with the castout value, or may skip levels based on program control. The control providing the skipping selection may be driven by a detector that analyzes load/store operations of a processor in order to produce efficient operation under changing memory use conditions.

Abstract: A multiprocessor data processing system includes an interconnect, a plurality of processing units coupled to the interconnect, and at least one system memory and a plurality of caches coupled to the plurality of processing units. A cache suitable for use in such a data processing system includes data storage containing multiple data granules and a number of state fields associated with the data granules. Each state field has a plurality of possible states including an OR state that indicates that an associated granule is consistent with corresponding data in the memory, that the associated data granule has unknown coherency with respect to other peer caches in the data processing system, and that the cache is responsible, among all of its peer caches that may store the associated data granule in a memory-consistent state with unknown coherency, for sourcing the data granule in response to a request.

Abstract: A multiprocessor data processing system includes an interconnect, a plurality of processing units coupled to the interconnect, and at least one system memory and a plurality of caches coupled to the plurality of processing units. A cache suitable for use in such a data processing system includes data storage containing multiple granules of data and a number of state fields associated with the granules of data. Each state field has a plurality of possible states including an O state indicating that an associated granule is consistent with corresponding data in the memory and has unknown coherency with respect to peer caches in the data processing system. The cache updates the state field from the O state to another of the plurality of states in response to a snooped transaction on the interconnect.

Abstract: A method and apparatus for casing out data within a cache memory hierarchy for a data processing system is disclosed. The data processing system has multiple processing units, each of the processing units having a multi-level cache memory hierarchy. The cache memory hierarchy includes a first cache and a second cache at a same cache level. Furthermore, the first cache and the second cache share a lower-level cache. In response to a castout write request from the first cache to the lower-level cache, the second cache aborts the data transfer for the castout write request if the second cache already has a copy of data of the castout write request. The coherency state of both the first and second caches are then updated.

Abstract: A method and apparatus for transmitting control signals within a hierarchial cache memory architecture of a data processing system is disclosed. The cache memory hierarchy includes multiple levels of cache memories, each level may have a different size and speed. In response to a processor request for information, a control command is sent to the cache memory hierarchy. The control command includes multiple control blocks. Beginning at the lowest possible cache level of the cache memory hierarchy, a determination is made whether or not there is a cache hit at a current level of the cache memory hierarchy. In response to a determination that there is not a cache hit at the current level, an abbreviated control command is sent to an upper cache level of the cache memory hierarchy, after a control block that corresponds to the current level is removed from the control command.

Abstract: A method and apparatus for casting out data within a cache memory hierarchy for a data processing system is disclosed. The data processing system has multiple processing units, each of the processing units having a multi-level cache memory hierarchy. In response to a castout write request from a cache memory to a non-inclusive lower-level cache memory within a cache memory hierarchy, the data transfer is aborted if the lower-level cache memory already has a copy of the data of the castout write. The coherency state of the lower-level cache memory is then updated, if necessary.

Abstract: A non-uniform memory access (NUMA) computer system includes a plurality of processing nodes coupled to a node interconnect. The plurality of processing nodes include at least a remote processing node, which contains a processor having an associated cache hierarchy, and a home processing node. The home processing node includes a shared system memory containing a plurality of memory granules and a coherence directory that indicates possible coherence states of copies of memory granules among the plurality of memory granules that are stored within at least one processing node other than the home processing node. If the processor within the remote processing node has a reservation for a memory granule among the plurality of memory granules that is not resident within the associated cache hierarchy, the coherence directory associates the memory granule with a coherence state indicating that the reserved memory granule may possibly be held non-exclusively at the remote processing node.

Abstract: A host bridge having a dataflow controller is provided. In a preferred embodiment, the host bridge contains a read command path which has a mechanism for requesting and receiving data from an upstream device. The host bridge also contains a write command path that has means for receiving data from a downstream device and for transmitting the received data to an upstream device. A target controller is used to receive the read and write commands from the downstream device and to steer the read command toward the read command path and the write command toward the write command path. A bus controller is also used to request control of an upstream bus before transmitting the request for data of the read command and transmitting the data of the write command.

Abstract: An apparatus and method of transmitting data from a PCI 2.1 compliant device is provided. PCI devices (i.e., PCI bridges) designed in accordance with the 2.1 PCI specification have a load data ordering feature that prohibits load data to bypass DMA write data in the bridge. The present apparatus and method allow load data to bypass DMA write data in the PCI bridge if the bridge is in an error state.

Abstract: A methodology and implementing system are provided in which PCI system configuration data is made available to a host X86 system CPU through an intermediate PowerPC system. A bus converter circuit connected between the X86 bus and the PowerPC bus is effective to translate configuration addresses between the X86 and the PowerPC system. A PCI host bridge arrangement includes a primary PCI host bridge circuit and a plurality of secondary peer PCI host bridge circuits. The primary host bridge circuit is effective to process configuration data requests from the bus converter circuit which are directed to any of the secondary PCI host bridge circuits.

Abstract: An apparatus and method of assigning communication channels for transmitting data through a host bridge are provided. In a preferred embodiment, a determination is made as to whether data is being transmitted through any one of the channels. If data is not being transmitted through one the channels, that channel is designated as the transmission channel for the present data transaction. If data is being transmitted through all of the channels, a least most recently used channel is selected as the data transmission channel. If however, more than one channel is not transmitting data, the data transmission channel assignments are made among the idle channels from a lowest channel number (e.g., channel 0) to a highest channel number (e.g., channel 7) or vice versa.

Abstract: A method and apparatus for snooping a host bridge. In a preferred embodiment, the apparatus includes a mechanism for loading data into the host bridge. Once the data is loaded, it is determined whether a copy of the data already resides in the host bridge. If so and the host bridge is not in the midst of a DMA transaction, the data will be immediately invalidated. If the host is in the midst of a DMA transaction, the data is then marked for invalidation.