Abstract: Apparatuses, systems, and methods are provided for scalable networking systems. An example system includes a plurality of core switches and a first stage patch panel associated with operation of a first set of network ports. In an operational configuration in which the first stage patch panel is coupled with the plurality of core switches, the first stage patch panel is configured to operatively couple the first set of network ports and a first portion of the plurality of core switches such that signals may pass therebetween. Furthermore, the first stage patch panel may preclude communication to a remaining portion of the plurality of core switches. The system may include a second stage patch panel associated with a second set of network ports that is operatively coupled with the plurality of core switches in the absence of the first stage patch panel so as to scale the networking system.

Abstract: An optoelectronic component may include a substrate, an electronic integrated circuit supported by the substrate, and a photonic integrated circuit supported by the substrate. The optoelectronic component may include a plurality of substrate interconnect connectors disposed on the substrate, a plurality of electronic integrated circuit interconnect connectors disposed on the electronic integrated circuit, and a plurality of photonic integrated circuit interconnect connectors disposed on the photonic integrated circuit. The optoelectronic component may include a first plurality of cable connectors, each cable connector connected to the substrate, the electronic integrated circuit, and the photonic integrated circuit via respective interconnect connectors. The first plurality of cable connectors may be configured to facilitate electrical communication between the substrate, the electronic integrated circuit, and the photonic integrated circuit.

Abstract: A data processing system with configurable processor chip buses. The processor chip is designed with a plurality of extended buses of which a number are configurable buses (i.e., capable of being allocated to one of several external components, particularly memory and other SMPs). The processor chip allows for the static allocation of these configurable buses to these external components, based primarily on vendor system design preferences.

Abstract: A data processing system with configurable processor chip buses. The processor chip is designed with a bus allocation unit and has a plurality of extended buses of which a number are configurable buses (i.e. may be dynamically allocated to any one of several external components, particularly memory and other SMPs). A priority determination of bandwidth requirements of the external components is made during system processing. Then the configurable buses are dynamically allocated to the external components based on their bandwidth requirement and/or the configuration which provides the best overall system efficiency.

Abstract: A method of maintaining cache coherency when a value is shared in one or more caches and an invalidation request for the corresponding memory block is issued, by sending a combined response to a requesting device indicating that it may proceed with a requested transaction, and reissuing the invalidation request in a background manner to any cache which responded with a shared/busy response. The invalidation request may be placed in a background kill queue, and later bus transactions compared with entries of the background kill queue to maintain the integrity of the target memory block. The requesting device's processor may continue to perform subsequent loads and stores to the line while other devices must wait for the background kill to complete before receiving control of the line.